Issues

• MPRV=1 page-permission checks use the real privilege instead of MPP — M-mode self-demotion silently broken (MmuPlugin.scala:319-322)

  SpinalHDL/NaxRiscv#183 · Filter by author kaci1928 opened on Oct 25, 2026

• Lockstep testbench never compares integer/float write destination register — wrong-rd bugs pass silently

  SpinalHDL/NaxRiscv#182 · Filter by author kaci1928 opened on Oct 16, 2026
  1

• JALR target silently truncated to 40 bits — fetch path has no canonicality/width check (BranchPlugin.scala:98)

  SpinalHDL/NaxRiscv#181 · Filter by author kaci1928 opened on Oct 16, 2026

• SLLIW/SRLIW/SRAIW decode masks ignore instr[25] (shamt[5]): reserved encodings execute instead of trapping (Rvi.scala:44-46)

  SpinalHDL/NaxRiscv#180 · Filter by author kaci1928 opened on Oct 16, 2026

• Non-canonical Sv39 virtual addresses are not faulted — effective address silently truncated to 40 bits (Lsu2Plugin.scala:116)

  SpinalHDL/NaxRiscv#179 · Filter by author kaci1928 opened on Oct 16, 2026

• Store to a vacant physical address via a valid Sv39 translation retires silently — translated path misses the memRange/IO PMA check (MmuPlugin.scala:323)

  SpinalHDL/NaxRiscv#178 · Filter by author kaci1928 opened on Oct 16, 2026

• MMU access faults are reported as page faults: mcause=13/15 instead of 5/7 (also when paging is off)

  SpinalHDL/NaxRiscv#177 · Filter by author kaci1928 opened on Oct 15, 2026

• fmin.d/fmax.d(subnormal, ±0.0) write back the wrong value — compare's rs1Equal ignores FloatMode: ±0 and MSB-only subnormal collide as (sign,exp,fraction) tuples (FpuCore.scala:530)

  SpinalHDL/NaxRiscv#176 · Filter by author kaci1928 opened on Oct 13, 2026

• Core stalls when data FIFO is enabled in Vivado AXI Interconnect

  SpinalHDL/NaxRiscv#171 · Filter by author littlewhi opened on Oct 7, 2026

• fcvt.d.s with a dynamic rounding mode and reserved frm is executed instead of raising illegal-instruction

  SpinalHDL/NaxRiscv#170 · Filter by author wndmll643 opened on Sep 5, 2026

• MMU page-table-walk pointers are truncated to physicalWidth with no out-of-range access-fault

  SpinalHDL/NaxRiscv#168 · Filter by author wndmll643 opened on Aug 13, 2026

• FP comparisons (feq.s/fle.s/flt.s) treat subnormal operands as equal to zero

  SpinalHDL/NaxRiscv#167 · Filter by author wndmll643 opened on Aug 4, 2026

• fcvt.d.w/fcvt.d.wu with rm=DYN and a reserved frm execute instead of raising illegal-instruction

  SpinalHDL/NaxRiscv#166 · Filter by author wndmll643 opened on Aug 2, 2026

• About simulation

  SpinalHDL/NaxRiscv#165 · Filter by author littlewhi opened on May 23, 2026
  2

• VCU118 2 GB memory or more

  SpinalHDL/NaxRiscv#163 · Filter by author XC1a opened on Mar 18, 2026
  6

• Inconsistencies Observed When Accessing Certain CSRs

  SpinalHDL/NaxRiscv#160 · Filter by author fly-1011 opened on Dec 8, 2025

• LSU issue

  SpinalHDL/NaxRiscv#147 · Filter by author bantierr opened on Oct 15, 2025
  7

• Interrupt handle problem when debug

  SpinalHDL/NaxRiscv#146 · Filter by author HaroldZ32 opened on Aug 15, 2025
  5

• Error while doing sbt "runMain naxriscv.Gen"

  SpinalHDL/NaxRiscv#140 · Filter by author Rishik-Y opened on Mar 12, 2025
  9

• CachePlugin with wayCount=1 gets eventually stuck loading the same data

  SpinalHDL/NaxRiscv#131 · Filter by author 7FM opened on Feb 4, 2025
  12

• Multicore simulation and execution

  SpinalHDL/NaxRiscv#127 · Filter by author dennisdef opened on Nov 26, 2024
  11

• about the gen.scala and ifetch

  SpinalHDL/NaxRiscv#119 · Filter by author duanjiulon opened on Jul 17, 2024
  18

• Nax not trap on store fault

  SpinalHDL/NaxRiscv#116 · Filter by author atkarim opened on Jul 16, 2024
  5

• Does NaxRiscv update mtval after trap illegal_inst?

  SpinalHDL/NaxRiscv#107 · Filter by author zhangkanqi opened on May 31, 2024
  2

• about litex and dhrystone

  SpinalHDL/NaxRiscv#96 · Filter by author duanjiulon opened on Apr 30, 2024
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