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Merge branch 'v0.2' of https://github.com/PSI-Rockin/CorgiDS into v0.2
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Simon committed Jan 4, 2018
2 parents 83201f9 + a5b3d20 commit 0953fd6
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Showing 8 changed files with 158 additions and 47 deletions.
10 changes: 8 additions & 2 deletions src/arm9rw.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,8 @@ uint32_t Emulator::arm9_read_word(uint32_t address)
return gpu.read_bga<uint32_t>(address);
if (address >= VRAM_BGB_START && address < VRAM_OBJA_START)
return gpu.read_bgb<uint32_t>(address);
if (address >= VRAM_OBJA_START && address < VRAM_OBJB_START)
return gpu.read_obja<uint32_t>(address);
if (address >= VRAM_LCDC_A && address < VRAM_LCDC_END)
return gpu.read_lcdc<uint32_t>(address);
if (address >= OAM_START && address < GBA_ROM_START)
Expand Down Expand Up @@ -637,6 +639,7 @@ void Emulator::arm9_write_word(uint32_t address, uint32_t word)
return;
case 0x04000358:
//TODO: FOG_COLOR
gpu.set_FOG_COLOR(word);
return;
case 0x04000600:
gpu.set_GXSTAT(word);
Expand Down Expand Up @@ -735,9 +738,12 @@ void Emulator::arm9_write_word(uint32_t address, uint32_t word)
//TODO: EDGE_COLOR
if (address >= 0x04000330 && address < 0x04000340)
return;
//TODO: FOG_TABLE
if (address >= 0x04000360 && address < 0x04000380)
{
for (int i = 0; i < 4; i++)
gpu.set_FOG_TABLE(address + i, (word >> (i * 8)) & 0xFF);
return;
}
if (address >= 0x04000380 && address < 0x040003C0)
{
gpu.set_TOON_TABLE((address & 0x3F) >> 1, word & 0xFFFF);
Expand Down Expand Up @@ -1085,7 +1091,7 @@ void Emulator::arm9_write_halfword(uint32_t address, uint16_t halfword)
//TODO: CLRIMAGE_OFFSET
return;
case 0x0400035C:
//TODO: FOG_OFFSET
gpu.set_FOG_OFFSET(halfword);
return;
case 0x04001000:
gpu.set_DISPCNT_B_lo(halfword);
Expand Down
2 changes: 1 addition & 1 deletion src/bios.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ void BIOS::cpu_set(ARM_CPU &cpu)
if (cpu.get_id())
{
//Reject reads and writes to BIOS area
if (source < 0x4000 && dest < 0x4000)
if (source < 0x4000 || dest < 0x4000)
return;
}

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14 changes: 11 additions & 3 deletions src/cartridge.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,18 @@ int NDS_Cart::load_ROM(string file_name)
int file_size = get_file_size(ROM_name + ".sav");
if (file_size)
{
static const int save_sizes[7] =
{512, 1024 * 8, 1024 * 64, 1024 * 256, 1024 * 512, 1024 * 1024, 1024 * 1024 * 8};
save_file.read((char*)SPI_save, file_size);
//Round save size up to the closest option
for (int i = 0; i < 6; i++)
{
if (file_size > save_sizes[i] && file_size <= save_sizes[i + 1])
{
file_size = save_sizes[i + 1];
break;
}
}
save_size = file_size;
printf("Loaded save for %s successfully.\n", ROM_name.c_str());
printf("Save size: %d\n", save_size);
Expand Down Expand Up @@ -504,7 +515,6 @@ void NDS_Cart::set_AUXSPIDATA(uint8_t value)
break;
default:
printf("\nUnrecognized AUXSPI cmd %d", value);
exit(1);
}
}
else
Expand Down Expand Up @@ -651,8 +661,6 @@ void NDS_Cart::set_AUXSPIDATA(uint8_t value)
spi_addr = 0x100;
}
break;
default:
exit(1);
}
}
spi_params++;
Expand Down
33 changes: 23 additions & 10 deletions src/gpu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -217,8 +217,6 @@ uint16_t GPU::read_extpal_bgb(uint32_t address)
{
if (ADDR_IN_RANGE(0, VRAM_H_SIZE) && VRAMCNT_H.MST == 2)
reg |= *(uint16_t*)&VRAM_H[address & VRAM_H_MASK];
else
exit(1);
}
return reg;
}
Expand Down Expand Up @@ -272,14 +270,14 @@ void GPU::write_bga(uint32_t address, uint16_t halfword)
if (VRAMCNT_E.enabled)
*(uint16_t*)&VRAM_E[address & VRAM_E_MASK] = halfword;
}
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_BGA_START, f_offset) && VRAMCNT_F.MST == 1)
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_BGA_START + f_offset, VRAM_F_SIZE) && VRAMCNT_F.MST == 1)
{
if (VRAMCNT_F.enabled)
*(uint16_t*)&VRAM_F[address & VRAM_F_MASK] = halfword;
}
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_BGA_START, g_offset) && VRAMCNT_G.MST == 1)
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_BGA_START + g_offset, VRAM_G_SIZE) && VRAMCNT_G.MST == 1)
{
if (VRAMCNT_G.enabled)
*(uint16_t*)&VRAM_G[address & VRAM_G_MASK] = halfword;
Expand Down Expand Up @@ -324,14 +322,14 @@ void GPU::write_obja(uint32_t address, uint16_t halfword)
if (VRAMCNT_E.enabled)
*(uint16_t*)&VRAM_E[address & VRAM_E_MASK] = halfword;
}
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_OBJA_START, f_offset) && VRAMCNT_F.MST == 2)
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_OBJA_START + f_offset, VRAM_F_SIZE) && VRAMCNT_F.MST == 2)
{
if (VRAMCNT_F.enabled)
*(uint16_t*)&VRAM_F[address & VRAM_F_MASK] = halfword;
}
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_OBJA_START, g_offset) && VRAMCNT_G.MST == 2)
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_OBJA_START + g_offset, VRAM_G_SIZE) && VRAMCNT_G.MST == 2)
{
if (VRAMCNT_G.enabled)
*(uint16_t*)&VRAM_G[address & VRAM_G_MASK] = halfword;
Expand Down Expand Up @@ -991,6 +989,21 @@ void GPU::set_CLEAR_DEPTH(uint32_t word)
eng_3D.set_CLEAR_DEPTH(word);
}

void GPU::set_FOG_COLOR(uint32_t word)
{
eng_3D.set_FOG_COLOR(word);
}

void GPU::set_FOG_OFFSET(uint16_t halfword)
{
eng_3D.set_FOG_OFFSET(halfword);
}

void GPU::set_FOG_TABLE(uint32_t address, uint8_t byte)
{
eng_3D.set_FOG_TABLE(address, byte);
}

void GPU::set_MTX_MODE(uint32_t word)
{
eng_3D.set_MTX_MODE(word);
Expand Down
37 changes: 22 additions & 15 deletions src/gpu.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -276,6 +276,9 @@ class GPU

void set_CLEAR_COLOR(uint32_t word);
void set_CLEAR_DEPTH(uint32_t word);
void set_FOG_COLOR(uint32_t word);
void set_FOG_OFFSET(uint16_t halfword);
void set_FOG_TABLE(uint32_t address, uint8_t byte);
void set_MTX_MODE(uint32_t word);
void MTX_PUSH();
void MTX_POP(uint32_t word);
Expand Down Expand Up @@ -326,14 +329,14 @@ T GPU::read_bga(uint32_t address)
}
if (VRAMCNT_F.enabled && VRAMCNT_F.MST == 1)
{
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_BGA_START, f_offset))
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_BGA_START + f_offset, VRAM_F_SIZE))
reg |= *(T*)&VRAM_F[address & VRAM_F_MASK];
}
if (VRAMCNT_G.enabled && VRAMCNT_G.MST == 1)
{
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_BGA_START, g_offset))
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_BGA_START + g_offset, VRAM_G_SIZE))
reg |= *(T*)&VRAM_G[address & VRAM_G_MASK];
}
return reg;
Expand Down Expand Up @@ -372,11 +375,11 @@ T GPU::read_obja(uint32_t address)
reg |= *(T*)&VRAM_B[address & VRAM_B_MASK];
if (ADDR_IN_RANGE(VRAM_OBJA_START, VRAM_E_SIZE) && VRAMCNT_E.MST == 2)
reg |= *(T*)&VRAM_E[address & VRAM_E_MASK];
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_OBJA_START, f_offset) && VRAMCNT_F.MST == 2)
uint32_t f_offset = (VRAMCNT_F.offset & 0x1) * 0x4000 + (VRAMCNT_F.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_OBJA_START + f_offset, VRAM_F_SIZE) && VRAMCNT_F.MST == 2)
reg |= *(T*)&VRAM_F[address & VRAM_F_MASK];
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x10000;
if (ADDR_IN_RANGE(VRAM_OBJA_START, g_offset) && VRAMCNT_G.MST == 2)
uint32_t g_offset = (VRAMCNT_G.offset & 0x1) * 0x4000 + (VRAMCNT_G.offset & 0x2) * 0x8000;
if (ADDR_IN_RANGE(VRAM_OBJA_START + g_offset, VRAM_G_SIZE) && VRAMCNT_G.MST == 2)
reg |= *(T*)&VRAM_G[address & VRAM_G_MASK];
//printf("\n(OBJA READ) $%08X: $%04X", address, reg);
return reg;
Expand Down Expand Up @@ -412,19 +415,19 @@ T GPU::read_teximage(uint32_t address)
}
if (VRAMCNT_B.enabled)
{
uint32_t offset = VRAMCNT_B.offset * VRAM_A_SIZE;
uint32_t offset = VRAMCNT_B.offset * VRAM_B_SIZE;
if (ADDR_IN_RANGE(offset, VRAM_B_SIZE) && VRAMCNT_B.MST == 3)
reg |= *(T*)&VRAM_B[address & VRAM_B_MASK];
}
if (VRAMCNT_C.enabled)
{
uint32_t offset = VRAMCNT_C.offset * VRAM_A_SIZE;
uint32_t offset = VRAMCNT_C.offset * VRAM_C_SIZE;
if (ADDR_IN_RANGE(offset, VRAM_C_SIZE) && VRAMCNT_C.MST == 3)
reg |= *(T*)&VRAM_C[address & VRAM_C_MASK];
}
if (VRAMCNT_D.enabled)
{
uint32_t offset = VRAMCNT_D.offset * VRAM_A_SIZE;
uint32_t offset = VRAMCNT_D.offset * VRAM_D_SIZE;
if (ADDR_IN_RANGE(offset, VRAM_D_SIZE) && VRAMCNT_D.MST == 3)
reg |= *(T*)&VRAM_D[address & VRAM_D_MASK];
}
Expand Down Expand Up @@ -525,12 +528,14 @@ T GPU::read_ARM7(uint32_t address)
T reg = 0;
if (VRAMCNT_C.enabled)
{
if (ADDR_IN_RANGE(0x06000000 + VRAMCNT_C.offset * 0x20000, VRAM_C_SIZE) && VRAMCNT_C.MST == 2)
uint32_t offset = (VRAMCNT_C.offset & 0x1) * 0x20000;
if (ADDR_IN_RANGE(0x06000000 + offset, VRAM_C_SIZE) && VRAMCNT_C.MST == 2)
reg |= *(T*)&VRAM_C[address & VRAM_C_MASK];
}
if (VRAMCNT_D.enabled)
{
if (ADDR_IN_RANGE(0x06000000 + VRAMCNT_D.offset * 0x20000, VRAM_D_SIZE) && VRAMCNT_D.MST == 2)
uint32_t offset = (VRAMCNT_D.offset & 0x1) * 0x20000;
if (ADDR_IN_RANGE(0x06000000 + offset, VRAM_D_SIZE) && VRAMCNT_D.MST == 2)
reg |= *(T*)&VRAM_D[address & VRAM_D_MASK];
}
return reg;
Expand All @@ -541,12 +546,14 @@ void GPU::write_ARM7(uint32_t address, T value)
{
if (VRAMCNT_C.enabled)
{
if (ADDR_IN_RANGE(0x06000000 + VRAMCNT_C.offset * 0x20000, VRAM_C_SIZE) && VRAMCNT_C.MST == 2)
uint32_t offset = (VRAMCNT_C.offset & 0x1) * 0x20000;
if (ADDR_IN_RANGE(0x06000000 + offset, VRAM_C_SIZE) && VRAMCNT_C.MST == 2)
*(T*)&VRAM_C[address & VRAM_C_MASK] = value;
}
if (VRAMCNT_D.enabled)
{
if (ADDR_IN_RANGE(0x06000000 + VRAMCNT_D.offset * 0x20000, VRAM_D_SIZE) && VRAMCNT_D.MST == 2)
uint32_t offset = (VRAMCNT_D.offset & 0x1) * 0x20000;
if (ADDR_IN_RANGE(0x06000000 + offset, VRAM_D_SIZE) && VRAMCNT_D.MST == 2)
*(T*)&VRAM_D[address & VRAM_D_MASK] = value;
}
}
Expand Down
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