Pinned Loading

1. dualcore-riscv dualcore-riscv Public

   Forked from sarveshjoshi29/processor_hardwarelab

   A dual-core, 5-stage pipelined RV32IMA RISC-V SoC implemented in Verilog for the Nexys A7-100T FPGA. Features split L1 caches, hardware atomic operations (LR/SC), and a FastAPI web dashboard for re…

   Verilog 1

2. fleet-optimization-engine fleet-optimization-engine Public

   Forked from Ritesh-Raj-Singh/KRITI-Optimization

   A high-performance C++ algorithmic solver for Heterogeneous Fleet Routing and Dial-a-Ride Problems (DARP) utilizing ALNS, VNS, and Branch-and-Cut.

   C++ 1

3. cvm-compiler cvm-compiler Public

   An end-to-end Bytecode Compiler and Stack-Based Virtual Machine for a Mini-C++ subset, built from scratch in C++17.

   C++ 1

4. Netflix-Inventory-Management Netflix-Inventory-Management Public

   OOPS-Based Content Management Client

   C++

5. Bonus-Task-FEC Bonus-Task-FEC Public

   Jupyter Notebook

6. 3-Stage-Pipeline 3-Stage-Pipeline Public

   Verilog