-
Notifications
You must be signed in to change notification settings - Fork 0
Initial draft of a public API to navigate and manipulate VHDL syntax #1
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
base: master
Are you sure you want to change the base?
Conversation
This is opposed to the previous implementation where the leading trivia would only return the immediate leading trivia stored in the token, which could be confusing. To get the trivia between two tokens, the user would have to manually extract leading and trailing trivias for the current and the previous resp. next token.
Implement greedy name parsing
… into syntax-crate
Regarding your comment here: If you say, you want to generate them from some description you are also considering providing the description using some kind of text file (e.g. JSON, YAML, whatever), am I right? Sure, the That's how I could imagine a description using YAML. It's basically the same as your macro approach but in a separate file and probably more readable? Is that the direction you imagined, or am I way off? :) # `SignalDeclaration` is a sequence of nodes and tokens
# with an optional alternative and an optional sequence
SignalDeclaration:
sequence:
- keyword: Signal
- node: IdentifierList
- token: Colon
- node: SubtypeIndication
- optional: true
alternative:
- keyword: Register
- keyword: Bus
- optional: true
sequence:
- token: ColonEq
- node: Expression
- token: SemiColon
# `IdentifierList` is a repeated node of `Identifier`s,
# separated by a `Comma` token
IdentifierList:
repeat: "+"
separate_by:
token: Comma
sequence:
- token: Identifier
# Provide the implementations for these nodes manually
SubtypeIndication:
raw: true
Expression:
raw: true |
No description provided.