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Fixed ADC register defines #18

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e3be6d3
Fixed ADC register defines
jernejp21 Jul 21, 2022
393e535
HAL fix for register redefine
jernejp21 Sep 7, 2022
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151axx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151cxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151dxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp151fxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153axx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153cxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153dxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp153fxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157axx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157cxx_cm4.h
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360 changes: 180 additions & 180 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_ca7.h
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549 changes: 287 additions & 262 deletions Drivers/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp157dxx_cm4.h
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2 changes: 1 addition & 1 deletion Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h
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Original file line number Diff line number Diff line change
Expand Up @@ -682,7 +682,7 @@ typedef struct
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_VSENSEEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN | \
ADC_CCR_DAMDF | \
ADC_CCR_DELAY | \
Expand Down
14 changes: 7 additions & 7 deletions Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_adc.h
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Expand Up @@ -706,7 +706,7 @@ typedef struct
/* only by selecting the corresponding ADC internal channel. */
#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
#define LL_ADC_PATH_INTERNAL_VDDCORE (ADC2_OR_VDDCOREEN) /*!< ADC measurement path to internal channel Vddcore */
/**
Expand Down Expand Up @@ -2390,7 +2390,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO
}
else
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
}
}

Expand Down Expand Up @@ -2506,7 +2506,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
}

/**
Expand Down Expand Up @@ -5109,7 +5109,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));

MODIFY_REG(*preg, ADC_LTR1_LT1, AWDThresholdValue);
MODIFY_REG(*preg, ADC_LTR1_LTR1, AWDThresholdValue);
}

/**
Expand Down Expand Up @@ -5141,7 +5141,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));

return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LT1));
return (uint32_t)(READ_BIT(*preg, ADC_LTR1_LTR1));
}

/**
Expand Down Expand Up @@ -5284,7 +5284,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
*/
__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
{
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OSR_Pos))));
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
}

/**
Expand All @@ -5296,7 +5296,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
{
return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OSR))+(1UL << ADC_CFGR2_OSR_Pos)) >> ADC_CFGR2_OSR_Pos);
return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
}

/**
Expand Down
28 changes: 14 additions & 14 deletions Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c
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Expand Up @@ -315,7 +315,7 @@
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */

#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */

Expand Down Expand Up @@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
ADC_CFGR2_ROVSE |
((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.Oversampling.OversamplingStopReset);
Expand Down Expand Up @@ -789,16 +789,16 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);

/* Reset register LTR1 and HTR1 */
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LTR1);
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HTR1);

/* Reset register LTR2 and HTR2*/
CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LTR2);
CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HTR2);

/* Reset register LTR3 and HTR3 */
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2);
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2);
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LTR2);
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HTR2);

/* Reset register SQR1 */
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
Expand Down Expand Up @@ -3028,8 +3028,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);

/* Set the high and low thresholds */
MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmp_awd_high_threshold_shifted);
MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LTR1 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HTR1 , tmp_awd_high_threshold_shifted);

/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
Expand Down Expand Up @@ -3098,14 +3098,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmp_awd_high_threshold_shifted);
MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LTR2 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HTR2 , tmp_awd_high_threshold_shifted);
}
else
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmp_awd_high_threshold_shifted);
MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LTR3 , tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HTR3 , tmp_awd_high_threshold_shifted);
}

if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
Expand Down
2 changes: 1 addition & 1 deletion Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c
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Expand Up @@ -2009,7 +2009,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
ADC_CFGR2_OVSR |
ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE |
((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
((pConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
pConfigInjected->InjecOversampling.RightBitShift
);
}
Expand Down
12 changes: 6 additions & 6 deletions Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -632,13 +632,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
);

/* Reset register TR1 */
CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LT1);
SET_BIT(ADCx->HTR1, ADC_HTR1_HT1);
CLEAR_BIT(ADCx->LTR1, ADC_LTR1_LTR1);
SET_BIT(ADCx->HTR1, ADC_HTR1_HTR1);

CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LT2);
SET_BIT(ADCx->HTR2, ADC_HTR2_HT2);
CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LT3);
SET_BIT(ADCx->HTR3, ADC_HTR3_HT3);
CLEAR_BIT(ADCx->LTR2, ADC_LTR2_LTR2);
SET_BIT(ADCx->HTR2, ADC_HTR2_HTR2);
CLEAR_BIT(ADCx->LTR3, ADC_LTR3_LTR3);
SET_BIT(ADCx->HTR3, ADC_HTR3_HTR3);

/* Reset register SQR1 */
CLEAR_BIT(ADCx->SQR1,
Expand Down