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🔭 I’m currently working on projects related to RTL Design, Functional and Formal Verification, FPGA prototyping of Digital designs ,etc.
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👨🎓 Specializing in Digital VLSI.
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💬 Ask me about Verilog, SystemVerilog, RISC-V, Cadence Jasper Gold, Cadence Genus, Xilinx vivado
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📫 How to reach me rakeshpatil1112369@gmail.com
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📄 My Resume https://drive.google.com/file/d/1CBDZj70uZW_VhVASF6FUZkr88PM51Yeb/view?usp=drive_link
