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Merge branch '1.8.4-rc'
2 parents 7464b3b + 8b604c9 commit b7bc7b7

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-38
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9 files changed

+49
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‎examples/thread_add_ipxact/test_thread_add_ipxact.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -700,8 +700,8 @@
700700
reg _tmp_2;
701701
reg _tmp_3;
702702
reg _tmp_4;
703-
assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
704-
assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
703+
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
704+
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
705705
reg [_saxi_maskwidth-1:0] _tmp_5;
706706
wire signed [32-1:0] _tmp_6;
707707
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :

‎examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1271,8 +1271,8 @@
12711271
reg _tmp_2;
12721272
reg _tmp_3;
12731273
reg _tmp_4;
1274-
assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
1275-
assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
1274+
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
1275+
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
12761276
reg [_saxi_maskwidth-1:0] _tmp_5;
12771277
wire signed [32-1:0] _tmp_6;
12781278
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :

‎examples/thread_ipxact/test_thread_ipxact.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -641,8 +641,8 @@
641641
reg _tmp_2;
642642
reg _tmp_3;
643643
reg _tmp_4;
644-
assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
645-
assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
644+
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
645+
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
646646
reg [_saxi_maskwidth-1:0] _tmp_5;
647647
wire signed [32-1:0] _tmp_6;
648648
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :

‎examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1268,8 +1268,8 @@
12681268
reg _tmp_2;
12691269
reg _tmp_3;
12701270
reg _tmp_4;
1271-
assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
1272-
assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
1271+
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
1272+
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
12731273
reg [_saxi_maskwidth-1:0] _tmp_5;
12741274
wire signed [32-1:0] _tmp_6;
12751275
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :

‎examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1281,8 +1281,8 @@
12811281
reg _tmp_2;
12821282
reg _tmp_3;
12831283
reg _tmp_4;
1284-
assign saxi_awready = (_saxi_register_fsm == 0) && !_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3;
1285-
assign saxi_arready = (_saxi_register_fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
1284+
assign saxi_awready = (_saxi_register_fsm == 0) && (!_tmp_1 && !_tmp_2 && !saxi_bvalid && _tmp_3);
1285+
assign saxi_arready = (_saxi_register_fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
12861286
reg [_saxi_maskwidth-1:0] _tmp_5;
12871287
wire signed [32-1:0] _tmp_6;
12881288
assign _tmp_6 = (_tmp_5 == 0)? _saxi_register_0 :

‎tests/extension/types_/axi_/slave_readwrite/test_types_axi_slave_readwrite.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -666,8 +666,8 @@
666666
reg _tmp_3;
667667
reg _tmp_4;
668668
reg _tmp_5;
669-
assign myaxi_awready = (fsm == 0) && !_tmp_2 && !_tmp_3 && !myaxi_bvalid && _tmp_4;
670-
assign myaxi_arready = (fsm == 0) && !_tmp_3 && !_tmp_2 && _tmp_5;
669+
assign myaxi_awready = (fsm == 0) && (!_tmp_2 && !_tmp_3 && !myaxi_bvalid && _tmp_4);
670+
assign myaxi_arready = (fsm == 0) && (!_tmp_3 && !_tmp_2 && _tmp_5 && !_tmp_4);
671671
reg [32-1:0] rdata;
672672
reg _myaxi_cond_0_1;
673673
assign myaxi_wready = fsm == 100;

‎tests/extension/types_/axi_/slave_readwrite_lite/test_types_axi_slave_readwrite_lite.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -479,8 +479,8 @@
479479
reg _tmp_2;
480480
reg _tmp_3;
481481
reg _tmp_4;
482-
assign myaxi_awready = (fsm == 0) && !_tmp_1 && !_tmp_2 && !myaxi_bvalid && _tmp_3;
483-
assign myaxi_arready = (fsm == 0) && !_tmp_2 && !_tmp_1 && _tmp_4;
482+
assign myaxi_awready = (fsm == 0) && (!_tmp_1 && !_tmp_2 && !myaxi_bvalid && _tmp_3);
483+
assign myaxi_arready = (fsm == 0) && (!_tmp_2 && !_tmp_1 && _tmp_4 && !_tmp_3);
484484
reg [32-1:0] rdata;
485485
reg _myaxi_cond_0_1;
486486
assign myaxi_wready = fsm == 100;

‎veriloggen/VERSION

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
1.9.2
1+
1.9.3

‎veriloggen/types/axi.py

Lines changed: 34 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1557,16 +1557,17 @@ def pull_request_counter(self, cond, counter=None):
15571557
prev_arvalid(self.raddr.arvalid)
15581558
)
15591559

1560-
writeval = (vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
1561-
vtypes.Not(self.wresp.bvalid),
1562-
prev_awvalid) if ready is None else
1563-
vtypes.Ands(ready, vtypes.Not(writevalid), vtypes.Not(readvalid),
1564-
vtypes.Not(self.wresp.bvalid),
1565-
prev_awvalid))
1566-
readval = (vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
1567-
prev_arvalid) if ready is None else
1568-
vtypes.Ands(ready, vtypes.Not(readvalid), vtypes.Not(writevalid),
1569-
prev_arvalid))
1560+
writeval = vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
1561+
vtypes.Not(self.wresp.bvalid),
1562+
prev_awvalid)
1563+
if ready is not None:
1564+
writeval = vtypes.Ands(ready, writeval)
1565+
1566+
readval = vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
1567+
prev_arvalid, vtypes.Not(prev_awvalid))
1568+
1569+
if ready is not None:
1570+
readval = vtypes.Ands(ready, readval)
15701571

15711572
_connect_ready(self.waddr.awready._get_module(),
15721573
self.waddr.awready, writeval)
@@ -2101,16 +2102,17 @@ def pull_request(self, cond):
21012102
prev_arvalid(self.raddr.arvalid)
21022103
)
21032104

2104-
writeval = (vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
2105-
vtypes.Not(self.wresp.bvalid),
2106-
prev_awvalid) if ready is None else
2107-
vtypes.Ands(ready, vtypes.Not(writevalid), vtypes.Not(readvalid),
2108-
vtypes.Not(self.wresp.bvalid),
2109-
prev_awvalid))
2110-
readval = (vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
2111-
prev_arvalid) if ready is None else
2112-
vtypes.Ands(ready, vtypes.Not(readvalid), vtypes.Not(writevalid),
2113-
prev_arvalid))
2105+
writeval = vtypes.Ands(vtypes.Not(writevalid), vtypes.Not(readvalid),
2106+
vtypes.Not(self.wresp.bvalid),
2107+
prev_awvalid)
2108+
if ready is not None:
2109+
writeval = vtypes.Ands(ready, writeval)
2110+
2111+
readval = vtypes.Ands(vtypes.Not(readvalid), vtypes.Not(writevalid),
2112+
prev_arvalid, vtypes.Not(prev_awvalid))
2113+
2114+
if ready is not None:
2115+
readval = vtypes.Ands(ready, readval)
21142116

21152117
_connect_ready(self.waddr.awready._get_module(),
21162118
self.waddr.awready, writeval)
@@ -2936,6 +2938,8 @@ def _make_img(filename, size, width, blksize=4096):
29362938
def _make_fsm(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
29372939
write_mode = 100
29382940
read_mode = 200
2941+
while read_mode <= write_mode + write_delay + 10:
2942+
read_mode += 100
29392943

29402944
self.fsm.If(self.waddr.awvalid).goto(write_mode)
29412945
self.fsm.If(self.raddr.arvalid).goto(read_mode)
@@ -3311,6 +3315,8 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
33113315
self._make_fsms(write_delay, read_delay, sleep, sub_sleep)
33123316

33133317
def _make_fsms(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
3318+
write_mode = 0
3319+
read_mode = 0
33143320

33153321
for i, (fsm, waddr, wdata, wresp, raddr, rdata) in enumerate(
33163322
zip(self.fsms, self.waddrs, self.wdatas, self.wresps, self.raddrs, self.rdatas)):
@@ -3350,9 +3356,14 @@ def _make_fsms(self, write_delay=10, read_delay=10, sleep=4, sub_sleep=4):
33503356
sleep_count(0)
33513357
)
33523358

3353-
offset = 1000 * i
3354-
write_mode = 100 + offset
3355-
read_mode = 200 + offset
3359+
offset = 100 * i
3360+
while offset <= read_mode + read_delay + 10:
3361+
offset += 100
3362+
3363+
write_mode = offset + 100
3364+
read_mode = offset + 200
3365+
while read_mode <= write_mode + write_delay + 10:
3366+
read_mode += 100
33563367

33573368
fsm.If(waddr.awvalid).goto(write_mode)
33583369
fsm.If(raddr.arvalid).goto(read_mode)

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