Strongly rewritten/reordered

.gitmodules

@@ -1,3 +1,3 @@
 [submodule "resources"]
 	path = resources
-	url = https://github.com/PyFPGA/resources
+	url = https://github.com/PyFPGA/resources.git

clean.sh

@@ -0,0 +1,9 @@
+#!/bin/bash
+
+set -e
+
+for DIR in */ ; do
+  if test -f "$DIR/Makefile"; then
+    make -C $DIR clean
+  fi
+done

ghdl-yosys/Makefile

@@ -0,0 +1,11 @@
+#!/usr/bin/make
+
+COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash
+
+all: vhdl vhdl-top vlog-top
+
+vhdl vhdl-top vlog-top:
+	$(COMMAND) [email protected]
+
+clean:
+	rm -fr *.cf

ghdl-yosys/vhdl-top.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+set -e
+
+DIR=../resources/mix
+
+yosys -Q -m ghdl -p "
+ghdl $DIR/top.vhdl -e;
+read_verilog $DIR/blink.v;
+synth -top Top
+"

ghdl-yosys/vhdl.sh

@@ -0,0 +1,18 @@
+#!/bin/bash
+
+set -e
+
+DIR=../resources/vhdl
+
+FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed"
+
+GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1"
+
+ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl
+ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl
+ghdl -a $FLAGS $DIR/top.vhdl
+
+yosys -Q -m ghdl -p "
+ghdl $FLAGS $GENERICS Top ARCH_SEL;
+synth -top Top
+"

ghdl-yosys/vlog-top.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+set -e
+
+DIR=../resources/mix
+
+yosys -Q -m ghdl -p "
+ghdl $DIR/blink.vhdl -e;
+read_verilog $DIR/top.v;
+synth -top Top
+"

ghdl/Makefile

@@ -0,0 +1,9 @@
+#!/usr/bin/make
+
+COMMAND=docker run --rm -it -v $$HOME:$$HOME -w $$PWD hdlc/ghdl:yosys bash
+
+vhdl:
+	$(COMMAND) [email protected]
+
+clean:
+	rm -fr *.cf

ghdl/README.md

@@ -0,0 +1,6 @@
+# Notes about GHDL
+
+> Last update: Nov 2021
+
+* Specify a REAL generic is not supported (`unhandled override for generic "rea"`)
+  * As a workaround, I set SKIP_REA

ghdl/vhdl.sh

@@ -0,0 +1,40 @@
+#!/bin/bash
+
+set -e
+
+DIR=../resources/vhdl
+
+FLAGS="--std=08 -fsynopsys -fexplicit -frelaxed"
+
+GENERICS="-gBOO=true -gINT=255 -gLOG='1' -gVEC="11111111" -gCHR='Z' -gSTR="WXYZ" -gSKIP_REA=1"
+
+###############################################################################
+# Alternative 1
+###############################################################################
+
+# This alternative is better to specify particular options per file
+
+ghdl -a $FLAGS --work=blink_lib $DIR/blink.vhdl
+ghdl -a $FLAGS --work=blink_lib $DIR/blink_pkg.vhdl
+ghdl -a $FLAGS $DIR/top.vhdl
+
+# --out=raw-vhdl generate a VHDL 93 netlist
+
+ghdl synth $FLAGS --out=raw-vhdl $GENERICS Top ARCH_SEL
+
+# This alternative creates .cf files
+
+rm -fr *.cf
+
+###############################################################################
+# Alternative 2
+###############################################################################
+
+# This alternative is more concise
+
+# --work=<LIBNAME> applies to the following files
+# --out=verilog generate a Verilog netlist
+
+ghdl synth $FLAGS --out=verilog $GENERICS \
+  --work=blink_lib $DIR/blink.vhdl $DIR/blink_pkg.vhdl \
+  --work=work $DIR/top.vhdl -e Top ARCH_SEL

vivado/Makefile

@@ -2,12 +2,14 @@
 
 COMMAND=vivado -mode batch -notrace -quiet -source
 
-flow params:
+all: vhdl vlog
+
+vhdl vlog prog detect:
 	$(COMMAND) [email protected]
 
 version:
 	echo "puts \$$tcl_version" | vivado -mode tcl -notrace -quiet
 
 clean:
 	rm -fr *.bit *.cache *.hw *.runs *.xpr *.jou *.ip_user_files
-	rm -fr *.html *.log *.txt *.xml .Xil
+	rm -fr *.html *.log *.txt *.xml .Xil *.zip

vivado/README.md

@@ -0,0 +1,17 @@
+# Notes about Vivado
+
+> Last update: Vivado 2021.2
+
+* FREQ=125MHz to match the employed clock of the ZYBO.
+
+VHDL:
+* Support to specify a REAL generic was added/fixed in the Vivado 2020.2 version
+  * https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-specify-a-REAL-generic-in-Vivado/m-p/1209088#M9581
+* Specify an architecture is supported, but not working
+  * https://support.xilinx.com/s/question/0D52E00006r9kHiSAI/specify-a-vhdl-architecture-seems-not-working
+  * As a workaround, I set SKIP_ARCH
+* Values are specified following Verilog notation.
+  * In case of character, is needed to specify the ASCII value
+
+Verilog:
+* `$finish` is ignored, but fortunatly `$error("some text")` produces the desired result.