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CPU topology v2 phase 5: add topology-aware preset generator foundation#11

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codex/cpu-topology-v2-phase-5-preset-generator
May 19, 2026
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CPU topology v2 phase 5: add topology-aware preset generator foundation#11
PrimeBuild-pc merged 2 commits into
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codex/cpu-topology-v2-phase-5-preset-generator

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@PrimeBuild-pc PrimeBuild-pc commented May 19, 2026

Summary

Adds the small foundation for topology-aware generated CPU presets without migrating UI, profiles, core masks, or runtime affinity apply paths.

  • Adds CpuPreset, ICpuPresetGenerator, CpuPresetGenerator, and CpuPresetGenerationOptions.
  • Registers the generator in service configuration for future phases.
  • Generates deterministic topology-derived presets only: all cores, physical/no-SMT when CoreIndex is available, all except CPU0, P/E core presets from EfficiencyClass, L3 group physical presets, best gaming suggestion, and safe compatibility.
  • Keeps preset generation based on CpuTopologySnapshot metadata only; no CPU SKU hardcoding.
  • Adds SourcePresetId for generated presets such as best-gaming, while keeping Reason user-facing.
  • Adds an X3D TODO only. X3D CCD-only presets are intentionally not generated until detection can be done with high confidence.

Out of scope

  • No UI changes.
  • No preset display/persistence work.
  • No profile or core mask migration.
  • No runtime affinity apply changes.
  • No ProcessService changes.
  • No registry/IFEO or priority guardrail changes.
  • No version change and no tag.

Tests

  • dotnet test "ThreadPilot_1.sln" --configuration Release --no-restore
  • Result: 216 passed, 0 failed, 0 skipped.

Existing warnings remain in unrelated test files: CS1998 in RetryPolicyServiceTests and CS0067 in ProcessMonitorManagerServiceTests.

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⚠️ Please install the 'codecov app svg image' to ensure uploads and comments are reliably processed by Codecov.

Codecov Report

❌ Patch coverage is 94.28571% with 14 lines in your changes missing coverage. Please review.

Files with missing lines Patch % Lines
Services/CpuPresetGenerator.cs 94.75% 3 Missing and 9 partials ⚠️
Services/CpuPresetGenerationOptions.cs 75.00% 1 Missing ⚠️
Services/ServiceConfiguration.cs 0.00% 1 Missing ⚠️

πŸ“’ Thoughts on this report? Let us know!

@PrimeBuild-pc PrimeBuild-pc marked this pull request as ready for review May 19, 2026 22:11
@PrimeBuild-pc PrimeBuild-pc merged commit 57676ae into main May 19, 2026
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@PrimeBuild-pc PrimeBuild-pc deleted the codex/cpu-topology-v2-phase-5-preset-generator branch May 19, 2026 22:11
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πŸ’‘ Codex Review

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Reviewed commit: 44bdc6f3bd

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? new[]
{
"p-cores-no-smt",
"l3-group-0-physical",
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P2 Badge Select L3 gaming source from generated cache groups

The best-gaming source list is hard-coded to l3-group-0-physical, but L3 presets are created with IDs derived from the actual cache index (l3-group-{group.Key}-physical). Because CpuTopologySnapshot does not normalize cache indexes, a topology with cache IDs like 2/3 will generate valid L3 presets that are never considered for best-gaming, causing an unnecessary fallback to broader presets and losing the intended cache-group-aware recommendation.

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SmtSiblingCount = topology.GetSmtSiblingGlobalIndexes(processor).Count,
};
})
.GroupBy(item => item.CoreIndex)
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P1 Badge Group physical-core selection by group-aware core key

SelectOneLogicalProcessorPerCore groups processors only by CoreIndex, which can collapse distinct cores when the same core index appears in different processor groups (a valid topology shape because CoreIndex uniqueness is not enforced by CpuTopologySnapshot). In that case, generated "physical" presets silently drop cores and can pin workloads to too few CPUs. The grouping key should include processor group context (for example (processor.Group, coreIndex)).

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