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target/ppc: Move {v,xx}sel and {v,xx}perm to decodetree, implement xxpermx #36

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target/ppc: Move {v,xx}sel and {v,xx}perm to decodetree, implement xxpermx #36

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7335758
target/ppc: Move vsel to decodetree
mferst Sep 8, 2021
cd4040c
target/ppc: move vperm/vpermr to decodetree
mferst Sep 8, 2021
60f567b
target/ppc: Move xxsel to decodetree
mferst Sep 14, 2021
a9a93b2
target/ppc: move xxperm/xxpermr to decodetree
mferst Sep 10, 2021
a652a49
target/ppc: Move xxpermdi to decodetree
mferst Sep 10, 2021
6e84abe
target/ppc: Implement xxpermx instruction
mferst Sep 8, 2021
be72a1f
fixup! target/ppc: move vperm/vpermr to decodetree
mferst Sep 24, 2021
cffb5ee
fixup! target/ppc: Move vsel to decodetree
mferst Sep 24, 2021
fcaa751
fixup! target/ppc: Implement xxpermx instruction
mferst Oct 15, 2021
a4a8160
fixup! target/ppc: Implement xxpermx instruction
mferst Oct 15, 2021
5af7d23
fixup! target/ppc: Move xxsel to decodetree
mferst Jan 4, 2022
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2 changes: 2 additions & 0 deletions target/ppc/insn32.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -408,6 +408,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN

VSEL 000100 ..... ..... ..... ..... 101010 @VA

# VSX Load/Store Instructions

LXV 111101 ..... ..... ............ . 001 @DQ_TSX
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12 changes: 12 additions & 0 deletions target/ppc/translate/vmx-impl.c.inc
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Expand Up @@ -1566,6 +1566,18 @@ static void gen_vpermr(DisasContext *ctx)
tcg_temp_free_ptr(rd);
}

static bool trans_VSEL(DisasContext *ctx, arg_VA *a)
{
REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
REQUIRE_VSX(ctx);

tcg_gen_gvec_bitsel(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->rc),
avr_full_offset(a->vrb), avr_full_offset(a->vra),
16, 16);

return true;
}

GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
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