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fix(csr): add CSR field and remove useless custom CSR #819

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merged 2 commits into from
Feb 28, 2025
Merged

fix(csr): add CSR field and remove useless custom CSR #819

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383cc25
fix(csr): add prefetch control by spfctl
sinceforYy Feb 28, 2025
3bb3755
fix(csr): remove useless custom csr
sinceforYy Feb 28, 2025
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15 changes: 6 additions & 9 deletions src/isa/riscv64/local-include/csr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,17 +33,15 @@
#define CUSTOM_CSR_SLVPREDCTL 0x5c2
#define CUSTOM_CSR_SMBLOCKCTL 0x5c3
#define CUSTOM_CSR_SRNCTL 0x5c4
#define CUSTOM_CSR_SFETCHCTL 0x9e0
#define CUSTOM_CSR_MCOREPWR 0xbc0
#define CUSTOM_CSR_MFLUSHPWR 0xbc1
#define CUSTOM_CSR_MBMC 0xbC2

#define CUSTOM_CSR_SBPCTL_WMASK 0x7f
#define CUSTOM_CSR_SPFCTL_WMASK 0x3ffff
#define CUSTOM_CSR_SPFCTL_WMASK 0x3fffff
#define CUSTOM_CSR_SLVPREDCTL_WMASK 0x1ff
#define CUSTOM_CSR_SMBLOCKCTL_WMASK 0x3ff
#define CUSTOM_CSR_SRNCTL_WMASK 0x5
#define CUSTOM_CSR_SFETCHCTL_WMASK 0x1
#define CUSTOM_CSR_MCOREPWR_WMASK 0x1
#define CUSTOM_CSR_MFLUSHPWR_WMASK 0x1

Expand Down Expand Up @@ -181,8 +179,7 @@
f(sbpctl , 0x5c0) \
f(spfctl , 0x5c1) \
f(slvpredctl, 0x5c2) \
f(smblockctl, 0x5c3) \
f(sfetchctl, 0x9e0)
f(smblockctl, 0x5c3)

#define CSRS_S_CUSTOM_1(f) \
CSRS_S_XIANGSHAN_CTRL(f)
Expand Down Expand Up @@ -1075,6 +1072,10 @@ CSR_STRUCT_START(spfctl)
uint64_t l1d_pf_active_stride : 6; // [15:10] L1D prefetch active page stride
uint64_t l1d_pf_enable_stride : 1; // [16] L1D prefetch enable stride
uint64_t l2_pf_store_only : 1; // [17] L2 pf store only
uint64_t l2_pf_recv_enable : 1; // [18] (Train L1, Prefetch L2) receive from sms
uint64_t l2_pf_pbop_enable : 1; // [19] (Train L1, Prefetch L2) PBOP
uint64_t l2_pf_vbop_enable : 1; // [20] (Train L1, Prefetch L2) VBOP
uint64_t l2_pf_tp_enable : 1; // [21] (Train L1, Prefetch L2) TP
CSR_STRUCT_END(spfctl)

CSR_STRUCT_START(slvpredctl)
Expand All @@ -1095,10 +1096,6 @@ CSR_STRUCT_START(smblockctl)
uint64_t hd_misalign_ld_enable : 1; // [9] Enable hardware load misalign.
CSR_STRUCT_END(smblockctl)

CSR_STRUCT_START(sfetchctl)
uint64_t icache_parity_enable : 1; // [0]
CSR_STRUCT_END(sfetchctl)

/** Supervisor Timer Register**/
#ifdef CONFIG_RV_SSTC
CSR_STRUCT_START(stimecmp)
Expand Down
7 changes: 4 additions & 3 deletions src/isa/riscv64/system/priv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -152,6 +152,10 @@ void init_custom_csr() {
spfctl->l1d_pf_active_stride = 30;
spfctl->l1d_pf_enable_stride = 1;
spfctl->l2_pf_store_only = 0;
spfctl->l2_pf_recv_enable = 1;
spfctl->l2_pf_pbop_enable = 1;
spfctl->l2_pf_vbop_enable = 1;
spfctl->l2_pf_tp_enable = 1;

slvpredctl->lvpred_disable = 0;
slvpredctl->no_spec_load = 0;
Expand All @@ -172,8 +176,6 @@ void init_custom_csr() {
srnctl->wfi_enable = 1;
#endif // CONFIG_RV_SVINVAL

sfetchctl->icache_parity_enable = 0;

mcorepwr->powerdown = 0;

mflushpwr->flushl2 = 0;
Expand Down Expand Up @@ -1828,7 +1830,6 @@ static void csr_write(uint32_t csrid, word_t src) {
case CUSTOM_CSR_SLVPREDCTL: *dest = src & CUSTOM_CSR_SLVPREDCTL_WMASK; break;
case CUSTOM_CSR_SMBLOCKCTL: *dest = src & CUSTOM_CSR_SMBLOCKCTL_WMASK; break;
IFDEF(CONFIG_RV_SVINVAL, case CUSTOM_CSR_SRNCTL: *dest = src & CUSTOM_CSR_SRNCTL_WMASK; break;)
case CUSTOM_CSR_SFETCHCTL: *dest = src & CUSTOM_CSR_SFETCHCTL_WMASK; break;

#ifdef CONFIG_RV_IMSIC
case CSR_STOPI: return;
Expand Down