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ideal model and value predictor support #297

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ideal model and value predictor support #297

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e1b2cb2
sim: Referenced the implementation of the exit callback
zybzzz Feb 20, 2025
1498675
arch-riscv,cpu: modify decoder to support ideal model
zybzzz Feb 20, 2025
70f2a92
cpu-o3: Add comments to the decode stage to improve readability.
zybzzz Feb 20, 2025
6b09494
configs,sim: Add the ideal model to the configuration file.
zybzzz Feb 20, 2025
8d7ec68
cpu: Added the basic interface for the ideal model
zybzzz Feb 20, 2025
385c521
cpu: Integrated the ideal model into BaseCPU
zybzzz Feb 20, 2025
75ec30b
cpu,cpu-o3: implementation of value predictor and ideal model
zybzzz Feb 20, 2025
1462604
util: Added a script to enable the ideal model
zybzzz Feb 20, 2025
16cc73c
cpu: remove duplicate export of stats in estride
zybzzz Feb 27, 2025
1b5a95e
cpu: add stats for ideal value predictor
zybzzz Feb 27, 2025
13091f7
cpu,cpu-o3:ideal model support noisasquash
zybzzz Feb 28, 2025
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18 changes: 18 additions & 0 deletions configs/common/Options.py
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Original file line number Diff line number Diff line change
Expand Up @@ -655,3 +655,21 @@ def addXiangshanFSOptions(parser):
default=None,
help="The shared lib file used to do difftest")

# Ideal model option
parser.add_argument("--enable-ideal-model",
action="store_true",
help="use NEMU-ideal-model as ideal model")

parser.add_argument("--ideal-model-so",
action="store",
default=None,
help="The shared lib file which provide ideal model for DSE")

parser.add_argument("--im-intaddvp",
action="store_true",
help="enable idael model for int add instructions value prediction")

parser.add_argument("--im-scalarlvp",
action="store_true",
help="enable ideal model scalar load value prediction")

34 changes: 34 additions & 0 deletions configs/common/XSConfig.py
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Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,16 @@ def config_xiangshan_inputs(args: argparse.Namespace, sys):
# use relative path to find the dramsim3 ini file, from configs/common/ to root
root_dir = os.path.dirname(os.path.dirname(os.path.dirname(__file__)))
args.dramsim3_ini = os.path.join(root_dir, 'ext/dramsim3/xiangshan_configs/xiangshan_DDR4_8Gb_x8_3200_2ch.ini')


# config ideal model
if args.enable_ideal_model:
if 'IDEAL_REF_SO' in os.environ:
args.ideal_model_so = os.environ['IDEAL_REF_SO']
print("Obtained ideal model from IDEAL_REF_SO: ", args.ideal_model_so)
else:
fatal("cant get ideal model so")

return gcpt_restorer, ref_so


Expand All @@ -128,3 +138,27 @@ def config_difftest(cpu_list, args, sys):
# cpu_list[0].enable_mem_dedup = True
cpu_list[0].enable_difftest = True
cpu_list[0].difftest_ref_so = args.difftest_ref_so

def config_ideal_model(cpu_list, args, sys):
if not args.enable_ideal_model:
return
else:
if len(cpu_list) > 1:
pass
else:
cpu_list[0].enable_ideal_model = True
cpu_list[0].ideal_model_so = args.ideal_model_so
print("in config ideal so : ", cpu_list[0].ideal_model_so)

# enable ideal model support type
ideal_model_support_type = []
if args.im_intaddvp:
ideal_model_support_type.append("IntAddVP")

if args.im_scalarlvp:
ideal_model_support_type.append("ScalarLVP")

print("test ideal model support type: ", ideal_model_support_type)
cpu_list[0].ideal_model_supports = ideal_model_support_type
print("ideal model support type: ", cpu_list[0].ideal_model_supports)

2 changes: 2 additions & 0 deletions configs/example/xiangshan.py
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Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,7 @@ def build_test_system(np, args):

test_sys.xiangshan_system = True
test_sys.enable_difftest = args.enable_difftest
test_sys.enable_ideal_model = args.enable_ideal_model

XSConfig.config_xiangshan_inputs(args, test_sys)

Expand Down Expand Up @@ -210,6 +211,7 @@ def build_test_system(np, args):
cpu.nemuSDimg = mmc.img_path

XSConfig.config_difftest(test_sys.cpu, args, test_sys)
XSConfig.config_ideal_model(test_sys.cpu, args, test_sys)

# configure vector
if args.enable_riscv_vector:
Expand Down
76 changes: 40 additions & 36 deletions src/arch/riscv/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>("zero instruction",
machInst);
Rp2 = sp + imm;
}}, uint64_t);
}}, uint64_t, {{IsIntAdd}});
format CompressedLoad {
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
Expand Down Expand Up @@ -172,7 +172,7 @@ decode QUADRANT default Unknown::unknown() {
}
}
Rc1_sd = Rc1_sd + imm;
}});
}}, int64_t, {{IsIntAdd}});
0x1: c_addiw({{
imm = CIMM5;
if (CIMM1 > 0)
Expand All @@ -183,7 +183,7 @@ decode QUADRANT default Unknown::unknown() {
"source reg x0", machInst);
}
Rc1_sw = (int32_t)(Rc1_sw + imm);
}});
}}, int64_t, {{IsIntAdd}});
0x2: c_li({{
imm = CIMM5;
if (CIMM1 > 0)
Expand All @@ -209,7 +209,7 @@ decode QUADRANT default Unknown::unknown() {
"immediate = 0", machInst);
}
sp_sd = sp_sd + imm;
}});
}}, int64_t, {{IsIntAdd}});
default: c_lui({{
imm = CIMM5 << 12;
if (CIMM1 > 0)
Expand Down Expand Up @@ -260,7 +260,7 @@ decode QUADRANT default Unknown::unknown() {
0x0: decode CFUNCT2LOW {
0x0: c_sub({{
Rp1 = Rp1 - Rp2;
}});
}},{{IsIntAdd}});
0x1: c_xor({{
Rp1 = Rp1 ^ Rp2;
}});
Expand All @@ -274,10 +274,10 @@ decode QUADRANT default Unknown::unknown() {
0x1: decode CFUNCT2LOW {
0x0: c_subw({{
Rp1_sd = (int32_t)Rp1_sd - Rp2_sw;
}});
}},{{IsIntAdd}});
0x1: c_addw({{
Rp1_sd = (int32_t)Rp1_sd + Rp2_sw;
}});
}},{{IsIntAdd}});
0x2: c_mul({{
Rp1_sd = (Rp1_sd * Rp2_sd);
}}, IntMultOp);
Expand Down Expand Up @@ -406,7 +406,7 @@ decode QUADRANT default Unknown::unknown() {
"source reg x1", machInst);
}
return std::make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsEBreak, IsIdealModelSystemOp, No_OpClass);
default: decode RC2 {
0x0: Jump::c_jalr({{
if (RC1 == 0) {
Expand All @@ -418,7 +418,7 @@ decode QUADRANT default Unknown::unknown() {
}}, IsIndirectControl, IsUncondControl, IsCall);
default: CompressedROp::c_add({{
Rc1_sd = Rc1_sd + Rc2_sd;
}});
}},{{IsIntAdd}});
}
}
}
Expand Down Expand Up @@ -772,7 +772,7 @@ decode QUADRANT default Unknown::unknown() {
}},int64_t, {{ imm = 0; }}, IsMov);
default: addi({{
Rd_sd = Rs1_sd + imm;
}});
}}, int64_t, {{imm = sext<12>(IMM12)}}, {{IsIntAdd}});
}
0x2: slti({{
Rd = (Rs1_sd < imm) ? 1 : 0;
Expand Down Expand Up @@ -835,7 +835,7 @@ decode QUADRANT default Unknown::unknown() {
format IOp {
0x0: addiw({{
Rd_sw = (int32_t)(Rs1_sw + imm);
}}, int32_t);
}}, int32_t, {{imm = sext<12>(IMM12)}}, {{IsIntAdd}});
0x1: decode FS3 {
0x0: slliw({{
Rd_sd = Rs1_sw << imm;
Expand Down Expand Up @@ -1169,10 +1169,10 @@ decode QUADRANT default Unknown::unknown() {
0x00: decode BS {
0x0: add({{
Rd = Rs1_sd + Rs2_sd;
}});
}}, {{IsIntAdd}});
0x1: sub({{
Rd = Rs1_sd - Rs2_sd;
}});
}}, {{IsIntAdd}});
}
0x01: decode BS {
0x0: mul({{
Expand Down Expand Up @@ -1394,16 +1394,16 @@ decode QUADRANT default Unknown::unknown() {
0x0: decode FUNCT7 {
0x0: addw({{
Rd_sd = Rs1_sw + Rs2_sw;
}});
}}, {{IsIntAdd}});
0x1: mulw({{
Rd_sd = (int32_t)(Rs1_sw*Rs2_sw);
}}, IntMultOp);
0x4: add_uw({{
Rd = Rs1_uw + Rs2;
}});
}}, {{IsIntAdd}});
0x20: subw({{
Rd_sd = Rs1_sw - Rs2_sw;
}});
}}, {{IsIntAdd}});
}
0x1: decode FUNCT7 {
0x0: sllw({{
Expand Down Expand Up @@ -4372,19 +4372,20 @@ decode QUADRANT default Unknown::unknown() {
0x0: ecall({{
return std::make_shared<SyscallFault>(
(PrivilegeMode)xc->readMiscReg(MISCREG_PRV));
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall, IsIdealModelSystemOp,
No_OpClass);
0x1: ebreak({{
return std::make_shared<BreakpointFault>(
xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsEBreak, IsIdealModelSystemOp, No_OpClass);
0x2: uret({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
status.uie = status.upie;
status.upie = 1;
xc->setMiscReg(MISCREG_STATUS, status);
NPC = xc->readMiscReg(MISCREG_UEPC);
}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
}}, IsSerializeAfter, IsNonSpeculative, IsReturn,
IsIdealModelSystemOp);
}
0x8: decode RS2 {
0x2: sret({{
Expand Down Expand Up @@ -4443,7 +4444,7 @@ decode QUADRANT default Unknown::unknown() {
}


}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
}}, IsSerializeAfter, IsNonSpeculative, IsReturn, IsIdealModelSystemOp);
0x5: wfi({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
auto pm = (PrivilegeMode)xc->readMiscReg(
Expand All @@ -4461,7 +4462,7 @@ decode QUADRANT default Unknown::unknown() {
machInst);
}
// don't do anything for now
}}, No_OpClass);
}}, IsIdealModelSystemOp, No_OpClass);
}
0x9: sfence_vma({{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
Expand All @@ -4472,7 +4473,7 @@ decode QUADRANT default Unknown::unknown() {
machInst);
}
xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
}}, IsNonSpeculative, IsSerializeAfter, IsIdealModelSystemOp, No_OpClass);
0x18: mret({{
if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
return std::make_shared<IllegalInstFault>(
Expand All @@ -4492,7 +4493,7 @@ decode QUADRANT default Unknown::unknown() {
NPC = xc->readMiscReg(MISCREG_MEPC);
xc->setMiscReg(MISCREG_VIRMODE,status_mpv);
}
}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
}}, IsSerializeAfter, IsNonSpeculative, IsReturn, IsIdealModelSystemOp);
0x31: priv({{
auto pm = (PrivilegeMode)xc->readMiscReg(
MISCREG_PRV);
Expand All @@ -4515,7 +4516,7 @@ decode QUADRANT default Unknown::unknown() {
"h-priv pm == prv_u", machInst);

}
}},IsNonSpeculative, IsSerializeAfter, No_OpClass);
}},IsNonSpeculative, IsSerializeAfter, IsIdealModelSystemOp, No_OpClass);
}
}
format CSROp {
Expand All @@ -4527,12 +4528,13 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data = Rs1;
write = RS1 != 0;
}}, IsUpdateMstatusSd,IsUpdateMstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateMstatusSd,IsUpdateMstatusSd,IsSerializeAfter,
IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
default:csrrw({{
Rd = data;
data = Rs1;
write = RS1 != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}
0x2: decode FUNCT12 {
0x100:csrrs_s({{
Expand All @@ -4542,7 +4544,8 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data |= Rs1;
write = RS1 != 0;
}}, IsUpdateVsstatusSd,IsUpdateMstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateVsstatusSd,IsUpdateMstatusSd,IsSerializeAfter, IsNonSpeculative,
IsIdealModelSystemOp, No_OpClass);
default:csrrs({{
auto Rs1_use = Rs1;
auto v = xc->readMiscReg(MISCREG_VIRMODE);
Expand All @@ -4551,7 +4554,7 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data |= Rs1_use;
write = RS1 != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}
0x3: decode FUNCT12 {
0x100:csrrc_s({{
Expand All @@ -4561,7 +4564,8 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data &= ~Rs1;
write = RS1 != 0;
}}, IsUpdateVsstatusSd,IsUpdateMstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateVsstatusSd,IsUpdateMstatusSd,IsSerializeAfter,
IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
default:csrrc({{
auto Rs1_use = Rs1;
auto v = xc->readMiscReg(MISCREG_VIRMODE);
Expand All @@ -4570,7 +4574,7 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data &= ~Rs1_use;
write = RS1 != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}
0x5: decode FUNCT12 {
0x100:csrrwi_s({{
Expand All @@ -4580,12 +4584,12 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data = uimm;
write = uimm != 0;
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
default:csrrwi({{
Rd = data;
data = uimm;
write = uimm != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}
0x6: decode FUNCT12 {
0x100:csrrsi_s({{
Expand All @@ -4595,7 +4599,7 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data |= uimm;
write = uimm != 0;
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
default:csrrsi({{
auto uimm_use = uimm;
auto v = xc->readMiscReg(MISCREG_VIRMODE);
Expand All @@ -4604,7 +4608,7 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data |= uimm_use;
write = uimm != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}
0x7: decode FUNCT12 {
0x100:csrrci_s({{
Expand All @@ -4614,12 +4618,12 @@ decode QUADRANT default Unknown::unknown() {
Rd = data;
data &= ~uimm;
write = uimm != 0;
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsUpdateVsstatusSd,IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
default:csrrci({{
Rd = data;
data &= ~uimm;
write = uimm != 0;
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
}}, IsSerializeAfter, IsNonSpeculative, IsIdealModelSystemOp, No_OpClass);
}

}
Expand Down
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