Rebase rvh 0905 #169

jueshiwenli · 2024-09-05T03:49:33Z

only test

Change-Id: I26add7336e515658b0bbdaebeb00bb2848826715

Change-Id: I5369768610a052299a3351b31677969d6a5d2f90

Change-Id: Id99aee3750b4c0c1e4882faab798efd003765e59

Change-Id: I376b0dc29ca9c889b58804eea4c6820b507d95b3

Change-Id: Id41c42de252f6630acc291d9aa24afe59ae3ee9b

Change-Id: I6fe28f5654b5312eb7a3d77013f6f99fd006fa93

Change-Id: Ibffd33bff95044db9ec4f7e28c2c60ff874a0bb8

Change-Id: Ib4b056c41e166ac374077b26567b31e9b681cfc6

Change-Id: I88ccd869c7b33d64aef57d3e84fdc8e947d1c770

Change-Id: I88f5910c6da05630eebd05cfcbe51ccffb376c92

In h-checkpoint ,we don't need to designate gcpt-restore Change-Id: I3433139c7e6b7f2774f3d9a1f7f0a5dbb874ea9e

Change-Id: Ic49497318b350438ad21b96a2a672d2feffbc247

Change-Id: Id2c6777612f53c511b563b886a9afca7f64a61b9

make pmp read with different mask Change-Id: If82e1f518e32c6e7da78d39664c124773930e9e8

Change-Id: Idaec4ec999785326520313c28c4af8d2a8d54fe7

Change-Id: I8b819a76c865bc7dfbdee0adec2a923f4f30b0d2

Change-Id: If8cb72df50610bd7eeaaee9790ff060798d72b50

Change-Id: I1e33d1ee58485febe6bc18701b5cdd9a43877371

Change-Id: I07fe1187cddb43ed2716c35e7400d39cad32d545

Change-Id: I0985c65e0a91777b76c865d0cd1b96609891d9be

Change-Id: I7ecc58f2006b4a6737c6cf9375779dd0a2c07464

Change-Id: If845f2fd261400fa981dfb947e48d5b3a86e4fb6

Change-Id: Ia25f935109225b1b0150893213a74855797d81c9

-when cpu.v =1 sret need update vsstatus -else need update v & hstatus -todo vsstatus.32 Change-Id: Ie7af67adae3c2fe337306517d0bec99ac4587056

-when in s mode judge whether is in hs -when in hs,update vsstatus v vscause vsepc Change-Id: I49f790f565fba928c751590084420b24f3a1caff

-fix bugs of write vsscratch -fix bugs of pc state Change-Id: I692366a494d2aeaff0e7f56035a6440e51ea550a

when need translate tlb will check translate mode two stage translate mode : -VSstage -Gstage the translate times up to 12 times Change-Id: Ic4b62dbd047224b2badde9edbf14dd9a5b44d4a6

Change-Id: Id4f3aa6ebf393e70685637622cd3e3f700e723cb

Change-Id: I79010640937001e87dcf0ed1b559f53b39be33d8

Change-Id: If3b3d3af7df6d460c7e6e106f87f5348927ab3d3

-all stage entry need put highest level in vs & g stage Change-Id: I29512c1ec3b66004cc607b9f15da620a5dc36c1a

Change-Id: I322f9773600387282e5785e77da1dc235e33d6f0

Change-Id: Iefce3679ab430f19a7183b0d16de5b9da2ef05c0

fix bugs of hit in l1tln gstage gPaddr Change-Id: Ia834112fe8799ed023b36576336e72475471a719

-allstsge hit need to check vsPte -TODO: sfence update vsatp & hgatp Change-Id: Ifca8d4b07aa453c30634383925c35011ca4645cf

hfence.gvma will flush tlb with addr & hgatp hfence.vvma will flush tlb wuth addr & vsatp Change-Id: I9fb815b43cb1e3a66af74ef6e7bb75ed609f8ddd

-add h-difftest when pagefault -add stats of pagefault times Change-Id: I51bcd1ebf3d0e7eda91ab335e775e829ec030382

Change-Id: Ifdd38b47f6222c1ab6e285f46644b837dc80eb39

add h-l2tlb but have bugs Change-Id: Ic2893ea3ea4ced17914a760b28a6185e27c358ca

-remove store allstage in l2tlb Change-Id: I0375a30bfa1692109faba86b6943603bbba7d097

-fix compiling error -add update translatemode -when hit in finifhgva mode need to write ptevs Change-Id: I50b30fad400841ff605b6ed059b8f3d3534a45bb

fix bug of update htval when store g pagefault Change-Id: I34d3536ed1ac7a9c1710a4c3d2bb43ffd42d5d71

-when hit in h-l2tlb h_l2VSstageHitContinue, need to ptw -check gpaddr -change gpaddr cover condition Change-Id: I5016567cef82cd521dbdf71b8baafc092c10e25b

-fix bugs of addr check -fix bugs of inGstage symbol -fix bugs of hit in l2tlb & need continue ptw Change-Id: I9e2cc6a268eef489afd9df3d1cf939ee8580580d

Change-Id: Idfaec17dadc150f752c8c681d442940cb9c20eea

when hit in h-l2tlb the resulkt will be send after set cycle Change-Id: If84510bcfe19bdda79923102bdf1f66caee01eab

Change-Id: I61fc8d9d73e33e4bcbff7c5e80fa974482437acf

Change-Id: I52487beb5e23aaf26f0e0db8b44a4804554526c9

-check tlb before ptw send request in vsstage Change-Id: Icebf3b67f8aa04b0577a4f80f20fdac135d8a3ee

Change-Id: Ibf39612734e9ec64bfef3231c4732989a910ff9c

Change-Id: I842f48f4c78bd1f1b4dbe7b591a466beb924e167

Change-Id: Iaaea75a53f61f8b2c911e6f1a12f4c4736fce8df

Change-Id: I1c0a8d03423e2dcb67db9e0a119c8720aed1f3a5

Change-Id: I38151b772d3612475463c4e0b6ad1676a9c47a12

Change-Id: I27cdfd1370d1e702c69cc68ba395f4ef1de82dc8

-default off h csr diff -add switch to enable enabledifftesInstTrace Change-Id: I91433e72310c8311dace7064ae0c0c3f6c71ed34

Change-Id: I622714e22df3f383ca95620dd3e0680604b8f332

shinezyy and others added 30 commits September 5, 2024 11:32

arch-riscv: add RISCV-H extension CSRs, WIP

56d1314

arch-riscv: set misa with H-ext

67931c8

Change-Id: I26add7336e515658b0bbdaebeb00bb2848826715

arch-riscv: fix bug of pmp

8ab096f

Change-Id: I5369768610a052299a3351b31677969d6a5d2f90

arch-riscv: add mhpmcounter

a4bdebd

Change-Id: Id99aee3750b4c0c1e4882faab798efd003765e59

arch-riscv: add mcountinhibit & fix bug of mcounteren

3874bd5

Change-Id: I376b0dc29ca9c889b58804eea4c6820b507d95b3

arch-riscv: add menvcfg

51c0400

Change-Id: Id41c42de252f6630acc291d9aa24afe59ae3ee9b

dev: Add nemu plic

24cff29

Change-Id: I6fe28f5654b5312eb7a3d77013f6f99fd006fa93

arch-riscv: make mideleg adapt h-ext

571c5a4

Change-Id: Ibffd33bff95044db9ec4f7e28c2c60ff874a0bb8

arch-riscv: add hfence.gvma

e2833d5

Change-Id: Ib4b056c41e166ac374077b26567b31e9b681cfc6

arch-riscv: make satp only adapt sv39

9d37208

Change-Id: I88ccd869c7b33d64aef57d3e84fdc8e947d1c770

dev: add plic read

def74c2

Change-Id: I88f5910c6da05630eebd05cfcbe51ccffb376c92

sim: change gcpt-restore config

c528f63

In h-checkpoint ,we don't need to designate gcpt-restore Change-Id: I3433139c7e6b7f2774f3d9a1f7f0a5dbb874ea9e

arch-riscv: make mstatus_mask the same as nemu

bc62f01

Change-Id: Ic49497318b350438ad21b96a2a672d2feffbc247

arch-riscv: make mie_mask same as nemu

f183d72

Change-Id: Id2c6777612f53c511b563b886a9afca7f64a61b9

arch-riscv: fix pmp bugs

732b80c

make pmp read with different mask Change-Id: If82e1f518e32c6e7da78d39664c124773930e9e8

arch-riscv: add hstatus

7479b8e

Change-Id: Idaec4ec999785326520313c28c4af8d2a8d54fe7

arch-riscv: fix bug of vsstatus & add h difftest

0f61829

Change-Id: I8b819a76c865bc7dfbdee0adec2a923f4f30b0d2

arch-riscv: add hie

4f271c7

Change-Id: If8cb72df50610bd7eeaaee9790ff060798d72b50

arch-riscv: open virtualization mode

863ec6a

Change-Id: I1e33d1ee58485febe6bc18701b5cdd9a43877371

arch-riscv: fix bugs of mstatus & vir mode

e9df80b

Change-Id: I07fe1187cddb43ed2716c35e7400d39cad32d545

arch-riscv: fix bugs of mastatus mask

9d30960

Change-Id: I0985c65e0a91777b76c865d0cd1b96609891d9be

arch-riscv: fix bugs of hstatus & virt mode

e7ab36f

Change-Id: I7ecc58f2006b4a6737c6cf9375779dd0a2c07464

arch-riscv: fix bugs of write hstatus

2c3a14e

Change-Id: If845f2fd261400fa981dfb947e48d5b3a86e4fb6

arch-riscv: fix bugs of write h csr

10ca306

Change-Id: Ia25f935109225b1b0150893213a74855797d81c9

arch-riscv: fix bugs of sret

cca1e62

-when cpu.v =1 sret need update vsstatus -else need update v & hstatus -todo vsstatus.32 Change-Id: Ie7af67adae3c2fe337306517d0bec99ac4587056

arch-riscv: fix bugs of pf

d299b9e

-when in s mode judge whether is in hs -when in hs,update vsstatus v vscause vsepc Change-Id: I49f790f565fba928c751590084420b24f3a1caff

arch-riscv: fix bugs of hsmode

76322a7

-fix bugs of write vsscratch -fix bugs of pc state Change-Id: I692366a494d2aeaff0e7f56035a6440e51ea550a

arch-riscv: add two stage translate mode

44e7e24

when need translate tlb will check translate mode two stage translate mode : -VSstage -Gstage the translate times up to 12 times Change-Id: Ic4b62dbd047224b2badde9edbf14dd9a5b44d4a6

arch-riscv: fix bugs of ptw

93f9ae2

Change-Id: Id4f3aa6ebf393e70685637622cd3e3f700e723cb

arch-riscv: fix bugs of PTW & htval

65c5abf

Change-Id: I79010640937001e87dcf0ed1b559f53b39be33d8

jueshiwenli added 26 commits September 5, 2024 11:42

arch-riscv: add h l1tlb

6119a2d

Change-Id: If3b3d3af7df6d460c7e6e106f87f5348927ab3d3

arch-riscv: fix bugs of hit in l1tlb

61d0817

-all stage entry need put highest level in vs & g stage Change-Id: I29512c1ec3b66004cc607b9f15da620a5dc36c1a

arch-riscv: fix bugs of vsatp0mode gpaddr

8be05ef

Change-Id: I322f9773600387282e5785e77da1dc235e33d6f0

arch-riscv: fix bugs of ptw & h l1tlb

5647864

Change-Id: Iefce3679ab430f19a7183b0d16de5b9da2ef05c0

arch-riscv: fix bugs of h l1tlb

298dedc

fix bugs of hit in l1tln gstage gPaddr Change-Id: Ia834112fe8799ed023b36576336e72475471a719

arch-riscv: fix bug of h-l1tlb

52b2a74

-allstsge hit need to check vsPte -TODO: sfence update vsatp & hgatp Change-Id: Ifca8d4b07aa453c30634383925c35011ca4645cf

arch-riscv: fix bugs of hfence

0824254

hfence.gvma will flush tlb with addr & hgatp hfence.vvma will flush tlb wuth addr & vsatp Change-Id: I9fb815b43cb1e3a66af74ef6e7bb75ed609f8ddd

cpu: fix bugs of difftest

7869b16

-add h-difftest when pagefault -add stats of pagefault times Change-Id: I51bcd1ebf3d0e7eda91ab335e775e829ec030382

arch-riscv: clean h-l1tlb code

b746584

Change-Id: Ifdd38b47f6222c1ab6e285f46644b837dc80eb39

arch-riscv: add h-l2tlb

062135f

add h-l2tlb but have bugs Change-Id: Ic2893ea3ea4ced17914a760b28a6185e27c358ca

arch-riscv: fix bugs of l2tlb

9a2de2f

-remove store allstage in l2tlb Change-Id: I0375a30bfa1692109faba86b6943603bbba7d097

arch-riscv: fix bugs of l2tlb

5d32437

-fix compiling error -add update translatemode -when hit in finifhgva mode need to write ptevs Change-Id: I50b30fad400841ff605b6ed059b8f3d3534a45bb

arch-riscv: fix bug of update htval

4099e43

fix bug of update htval when store g pagefault Change-Id: I34d3536ed1ac7a9c1710a4c3d2bb43ffd42d5d71

arch-riscv: fix bugs of l2tlb & ptw

575887f

-when hit in h-l2tlb h_l2VSstageHitContinue, need to ptw -check gpaddr -change gpaddr cover condition Change-Id: I5016567cef82cd521dbdf71b8baafc092c10e25b

arch-riscv: fix bugs of h-l2tlb

feeef53

-fix bugs of addr check -fix bugs of inGstage symbol -fix bugs of hit in l2tlb & need continue ptw Change-Id: I9e2cc6a268eef489afd9df3d1cf939ee8580580d

arch-riscv: add h-l2tlb hfence

b7034ae

Change-Id: Idfaec17dadc150f752c8c681d442940cb9c20eea

arch-riscv: add h-l2tlb delay

ea24a44

when hit in h-l2tlb the resulkt will be send after set cycle Change-Id: If84510bcfe19bdda79923102bdf1f66caee01eab

arch-riscv: fix buf of h-l2tlb

b9e6bcd

Change-Id: I61fc8d9d73e33e4bcbff7c5e80fa974482437acf

arch-riscv: check tlb before ptw send request

0d07da8

Change-Id: I52487beb5e23aaf26f0e0db8b44a4804554526c9

arch-riscv: add tlb check

a146047

-check tlb before ptw send request in vsstage Change-Id: Icebf3b67f8aa04b0577a4f80f20fdac135d8a3ee

arch-riscv: fix bugs of pmp

a733104

Change-Id: Ibf39612734e9ec64bfef3231c4732989a910ff9c

arch-riscv: update csr mask

737fd43

Change-Id: I842f48f4c78bd1f1b4dbe7b591a466beb924e167

mem: fix bugs of physical size

aeab611

Change-Id: Iaaea75a53f61f8b2c911e6f1a12f4c4736fce8df

misc: update ci path

35e890f

Change-Id: I1c0a8d03423e2dcb67db9e0a119c8720aed1f3a5

arch-riscv: fix bugs of h-l2tlb

1702720

Change-Id: I38151b772d3612475463c4e0b6ad1676a9c47a12

arch-riscv: fix bugs of MTINST & MTVAL2

e77a708

Change-Id: I27cdfd1370d1e702c69cc68ba395f4ef1de82dc8

jueshiwenli force-pushed the rebase-rvh-0905 branch from 78d21c2 to e77a708 Compare September 5, 2024 06:49

jueshiwenli added 2 commits September 6, 2024 11:48

cpu: update difftest display

54e2548

-default off h csr diff -add switch to enable enabledifftesInstTrace Change-Id: I91433e72310c8311dace7064ae0c0c3f6c71ed34

misc: update ref & restore path

4923df3

Change-Id: I622714e22df3f383ca95620dd3e0680604b8f332

jueshiwenli closed this Sep 12, 2024

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Rebase rvh 0905 #169

Rebase rvh 0905 #169

jueshiwenli commented Sep 5, 2024

Rebase rvh 0905 #169

Rebase rvh 0905 #169

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jueshiwenli commented Sep 5, 2024