cpu-o3: change the condition of dispatchInst

 now it needs all iqs to be ready

Change-Id: I6efa102dd03a120b8f8d5d63c554445fab7d3906

src/cpu/o3/iew.cc

@@ -1178,6 +1178,10 @@ IEW::dispatchInstFromDispQue(ThreadID tid)
     bool add_to_iq = false;
     int dis_num_inst = 0;
 
+    if (!CanDispatch(tid)){
+        return;
+    }
+
     for (int i = 0; i < NumDQ; i++) {
         int dispatched = 0;
         while (!dispQue[i].empty() && dispatched < dispWidth[i]) {
@@ -1311,6 +1315,12 @@ IEW::dispatchInstFromDispQue(ThreadID tid)
     iewStats.dispDist.sample(dis_num_inst);
 }
 
+bool
+IEW::CanDispatch(ThreadID tid)
+{
+    return scheduler->Allready();
+}
+
 void
 IEW::printAvailableInsts()
 {

src/cpu/o3/iew.hh

@@ -319,6 +319,9 @@ class IEW
      *  second, receive new inst from rename, store it to DQ
      */
     void dispatchInstFromDispQue(ThreadID tid);
+
+    bool CanDispatch(ThreadID tid);
+
     void classifyInstToDispQue(ThreadID tid);
 
     /** Executes instructions. In the case of memory operations, it informs the

src/cpu/o3/issue_queue.cc

@@ -833,6 +833,16 @@ Scheduler::ready(const DynInstPtr& inst)
     DPRINTF(Schedule, "IQ not ready, opclass: %s\n", enums::OpClassStrings[inst->opClass()]);
     return false;
 }
+bool
+Scheduler::Allready()
+{
+    for (auto iq :issueQues){
+        if (!iq->ready()) {
+            return false;
+        }
+    }
+    return true;
+}
 
 bool
 Scheduler::full(const DynInstPtr& inst)

src/cpu/o3/issue_queue.hh

@@ -276,6 +276,7 @@ class Scheduler : public SimObject
     void issueAndSelect();
     bool full(const DynInstPtr& inst);
     bool ready(const DynInstPtr& inst);
+    bool Allready();
     DynInstPtr getInstByDstReg(RegIndex flatIdx);
 
     void addProducer(const DynInstPtr& inst);