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core: imx: 8m phytec boards: increase CFG_DDR_SIZE #7526

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core: imx: 8m phytec boards: increase CFG_DDR_SIZE #7526

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12 changes: 8 additions & 4 deletions core/arch/arm/plat-imx/conf.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -408,14 +408,16 @@ CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
endif

ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
CFG_DDR_SIZE ?= 0x40000000
CFG_DDR_SIZE ?= UL(0x100000000)
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@sahilnxp sahilnxp Sep 15, 2025

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From 8MM and 8MP reference manual, DDR addresses are aligned as shown below:

Image

For the boards having more than, 3GB of memory, I think you need to define CFG_NSEC_DDR_1_BASE and CFG_NSEC_DDR_1_SIZE also.

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@ymoog ymoog Sep 17, 2025

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Forgot about that, thanks.

ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
CFG_DDR_SIZE ?= UL(0x180000000)
CFG_UART_BASE ?= UART2_BASE

Does the imx8mp evk have this problem as well, then?

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@sahilnxp sahilnxp Sep 22, 2025

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Yes imx8mp evk has same memory map like this one.

CFG_TZDRAM_START = 0x7e000000
CFG_UART_BASE ?= UART3_BASE
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_CORE_ARM64_PA_BITS,36)
endif

ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
CFG_DDR_SIZE ?= 0x80000000
CFG_DDR_SIZE ?= UL(0x100000000)
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@sahilnxp sahilnxp Sep 15, 2025

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Did you test with these changes on all 8m phytec platforms ?
Since tzc380.c is enabled on 8MM and 8MP platforms, and it takes CFG_DDR_SIZE in account while configuring the regions, I am not sure what impact this will have on TZC programming.
Can you please check this also.

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@ymoog ymoog Sep 17, 2025

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I tested that all boards boot and xtest runs successfully. Is there a specific test you recommend me to run or what I should check? I'll take a closer look at how tzc-380 works.

CFG_TZDRAM_START = 0xbe000000
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@sahilnxp sahilnxp Sep 15, 2025

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Hi @ymoog

From commit message, shared memory address will be in first 1GB memory, but this address is not in first 1GB of memory, please check.

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@ymoog ymoog Sep 17, 2025

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Hi @sahilnxp, thanks for calling that out. The phygate tauri does not exist as a 1GiB memory variant. I'll rework the commit message.

CFG_UART_BASE ?= UART3_BASE
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_CORE_ARM64_PA_BITS,36)
Expand All @@ -434,14 +436,16 @@ $(call force,CFG_CORE_ARM64_PA_BITS,36)
endif

ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
CFG_DDR_SIZE ?= 0x40000000
CFG_DDR_SIZE ?= UL(0x100000000)
CFG_TZDRAM_START = 0x7e000000
CFG_UART_BASE ?= UART4_BASE
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_CORE_ARM64_PA_BITS,36)
endif

ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
CFG_DDR_SIZE ?= 0x40000000
CFG_DDR_SIZE ?= UL(0x100000000)
CFG_TZDRAM_START = 0x7e000000
CFG_UART_BASE ?= UART1_BASE
$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
$(call force,CFG_CORE_ARM64_PA_BITS,36)
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