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@timlee0212 timlee0212 commented Oct 23, 2025

Summary by CodeRabbit

  • Bug Fixes

    • Enhanced performance of multi-GPU collective communication operations through kernel improvements across GPU architectures.
  • Tests

    • Re-enabled multi-GPU allreduce test to strengthen validation coverage for distributed communication scenarios.

Description

This PR fixed the accuracy issue in MNNVL Allreduce kernel on Hopper caused by wrong memory semantic used in the Hopper branch.

Test Coverage

tests/unittest/_torch/multi_gpu/test_mnnvl_allreduce.py

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@timlee0212 timlee0212 requested a review from a team as a code owner October 23, 2025 06:11
Signed-off-by: Shiyu Li <[email protected]>
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📝 Walkthrough

Walkthrough

The changes expand CUDA inline assembly support in mnnvlTwoShotAllreduceKernels to lower GPU architectures (from 700+) by adopting release-variant intrinsics, and enable a previously-skipped test in the mnnvl_allreduce test suite.

Changes

Cohort / File(s) Summary
CUDA kernel inline assembly support
cpp/tensorrt_llm/kernels/communicationKernels/mnnvlTwoShotAllreduceKernels.cu
Modified LamportFlags::cta_arrive to lower the GPU architecture threshold from >= 900 to >= 700 for inline assembly path selection; changed intrinsic from red.global.gpu.add.u32 to red.release.global.gpu.add.u32, enabling release-variant atomics on mid-range architectures.
Test suite
tests/unittest/_torch/multi_gpu/test_mnnvl_allreduce.py
Removed pytest.skip call from test_row_linear_residual_norm_fusion to enable test execution instead of skipping.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~12 minutes

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❌ Failed checks (1 warning)
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✅ Passed checks (2 passed)
Check name Status Explanation
Title Check ✅ Passed The PR title "[https://nvbugs/5597647][fix] Fix MNNVL Allreduce accuracy issue on Hopper" clearly and accurately summarizes the main change in the pull request. It follows the required format with a valid NVBugs ticket ID and the correct type indicator. The title is specific enough that a reviewer can immediately understand the primary change—fixing an accuracy issue in the MNNVL Allreduce kernel on Hopper architecture. The raw summary confirms this is indeed the central change, with modifications to the CUDA kernel's memory semantics for Hopper and enabling a previously skipped test.
Description Check ✅ Passed The pull request description includes all required sections from the template: a properly formatted title with NVBugs ID and fix type indicator, a Description section that clearly explains the issue (accuracy problem in MNNVL Allreduce kernel on Hopper caused by incorrect memory semantics) and the solution, an identified Test Coverage section listing the relevant test file, and a completed PR Checklist with a checkmark indicating review. While the Description section is relatively brief, it provides sufficient context about what was fixed and why, avoiding vagueness while remaining specific about the technical issue being addressed.
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/bot run --add-multi-gpu-test

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Actionable comments posted: 1

📜 Review details

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between f4e1cc7 and deac80f.

📒 Files selected for processing (2)
  • cpp/tensorrt_llm/kernels/communicationKernels/mnnvlTwoShotAllreduceKernels.cu (1 hunks)
  • tests/unittest/_torch/multi_gpu/test_mnnvl_allreduce.py (0 hunks)
💤 Files with no reviewable changes (1)
  • tests/unittest/_torch/multi_gpu/test_mnnvl_allreduce.py
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**/*.{h,hpp,hh,hxx,cpp,cxx,cc,cu,cuh}

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Comment on lines +120 to +121
#elif (defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 700))
asm volatile("red.release.global.gpu.add.u32 [%0], %1;" ::"l"(offset_access_ptr), "r"(1) : "memory");
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⚠️ Potential issue | 🔴 Critical

🧩 Analysis chain

Verify PTX instruction support and consider architectural consistency.

The addition of release memory semantics correctly fixes the synchronization issue by ensuring all prior memory writes are visible before the atomic counter increment. This is essential for the Lamport flag protocol's correctness.

However, several points require verification:

  1. PTX instruction support: The threshold change from sm_90 to sm_70 extends this path to Volta, Turing, and Ampere architectures. Verify that red.release.global.gpu.add.u32 is supported on sm_70-sm_89.

  2. Scope broader than PR title: The PR title mentions "Fix MNNVL Allreduce accuracy issue on Hopper", but this change affects all architectures >= sm_70. If the issue exists on these older architectures too, the PR description should reflect this broader impact.

  3. Architectural consistency: Other parts of the file still use __CUDA_ARCH__ >= 900 checks (lines 154, 217, 436 for cudaGridDependencySynchronize() and cudaTriggerProgrammaticLaunchCompletion()). Should the synchronization strategy be consistent across these checks?

Additionally, please search the web for PTX ISA documentation to confirm red.release.global.gpu.add.u32 support:


🏁 Script executed:

#!/bin/bash
# Verify PTX instruction support across architectures

# Search for documentation or comments about PTX instruction requirements
rg -n "red\.release\.global" --type=cu --type=cpp -C3

# Check if there are other uses of architecture-specific synchronization
rg -n "__CUDA_ARCH__.*>=.*(700|900|1000)" --type=cu --type=cpp -C2

# Look for any existing tests or validation of this instruction on different architectures
rg -n "sm_[0-9]+" --type=cu --type=cpp -g "*test*" -g "*mnnvl*" -C2

Length of output: 80


🌐 Web query:

PTX ISA red.release.global instruction support compute capability sm_70 sm_80

💡 Result:

Short answer: Yes — PTX reduction instructions with the .release (e.g., red.release.global.*) are supported on sm_70 and on sm_80 (sm_80 ≥ sm_70). The PTX docs show the .sem/.release qualifiers require compute capability sm_70 or higher, and sm_80 is a later target that includes those features. [1][2]

Sources:

  • NVIDIA PTX / Parallel Thread Execution target-ISA notes (.sem / .release require sm_70+). [1]
  • PTX ISA reference (examples and target notes; sm_80 is a supported target and includes qualifiers introduced for sm_70+). [2]


---

🏁 Script executed:

```shell
#!/bin/bash
# Find the file and examine architecture-specific checks
fd mnnvlTwoShotAllreduceKernels.cu -x cat {} | head -n 300

Length of output: 10462


🏁 Script executed:

#!/bin/bash
# Search for all __CUDA_ARCH__ comparisons in the file
fd mnnvlTwoShotAllreduceKernels.cu -x grep -n "__CUDA_ARCH__" {}

Length of output: 297


🏁 Script executed:

#!/bin/bash
# Check for other synchronization primitives and their arch requirements
fd mnnvlTwoShotAllreduceKernels.cu -x grep -n "cudaGridDependencySynchronize\|cudaTriggerProgrammaticLaunchCompletion\|red\." {}

Length of output: 429


Architectural mismatch: Grid dependency synchronization still requires sm_90+, making the code incomplete for sm_70-sm_89.

The PTX instruction red.release.global.gpu.add.u32 is confirmed supported on sm_70+, and the instruction change is technically correct.

However, the change reveals a critical architectural inconsistency:

The Lamport flag synchronization now extends to sm_70+ (Volta), but the grid dependency synchronization primitives remain sm_90+ only:

  • Line 155: cudaGridDependencySynchronize() — sm_90+ only
  • Line 218: cudaTriggerProgrammaticLaunchCompletion() — sm_90+ only
  • Line 460: cudaTriggerProgrammaticLaunchCompletion() — sm_90+ only

On sm_70-sm_89 GPUs, these lines are skipped, leaving the kernel without proper grid-level synchronization. Since cudaGridDependencySynchronize() is called at the start of the kernel (line 155) and cudaTriggerProgrammaticLaunchCompletion() at the end (line 218), skipping them breaks the synchronization protocol.

Required:
Either extend grid dependency synchronization support to sm_70+ to match the Lamport flag change, or explicitly document why this code path should only run on sm_90+. The current state creates undefined behavior on Volta-Ampere architectures.

🤖 Prompt for AI Agents
In cpp/tensorrt_llm/kernels/communicationKernels/mnnvlTwoShotAllreduceKernels.cu
around lines 120-121 (and related grid sync calls at ~155, ~218, ~460): the PTX
lamport flag update was extended to sm_70+, but the grid-dependency APIs
(cudaGridDependencySynchronize / cudaTriggerProgrammaticLaunchCompletion) are
still only enabled for sm_90+, leaving sm_70–sm_89 builds without grid-level
synchronization. Fix by either (A) extending the grid-dependency support to
sm_70+ to match the Lamport change (update the preprocessor/runtime arch checks
so the cudaGridDependencySynchronize and cudaTriggerProgrammaticLaunchCompletion
calls are enabled for >=700, or add a robust runtime arch check and enable them
when supported), or (B) explicitly restrict this whole codepath to sm_90+ and
add a clear compile-time/static-runtime guard plus a comment and error message
explaining that Volta/ampere (sm_70–sm_89) are unsupported; if choosing (A)
provide a safe fallback for devices lacking those APIs (implement equivalent
programmatic-launch completion using the existing Lamport flags/global
atomics/spin-wait protocol) and ensure all three sync points (start at ~155, end
at ~218 and ~460) are consistently handled for the same architectures.

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PR_Github #22254 [ run ] triggered by Bot. Commit: deac80f

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PR_Github #22254 [ run ] completed with state FAILURE. Commit: deac80f
/LLM/release-1.1/L0_MergeRequest_PR pipeline #238 completed with status: 'FAILURE'

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/bot run --add-multi-gpu-test

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PR_Github #22312 [ run ] triggered by Bot. Commit: deac80f

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PR_Github #22312 [ run ] completed with state SUCCESS. Commit: deac80f
/LLM/release-1.1/L0_MergeRequest_PR pipeline #243 completed with status: 'FAILURE'

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