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Porting U Boot
UART0 is the default UART interface, and is defined in armada_38x.h under include/configs:
#define CONFIG_SYS_DUART_CHAN 0
To set UART1 as the default UART interface instead of UART0, change the appropriate definition to 1:
#define CONFIG_SYS_DUART_CHAN 1
NOTE: The relevant UART MPP pins must be set accordingly (see Section MPP Configuration in the "Porting Hardware Adaptation Layer" Wiki: MPP Configuration).
The parameters are configured in include/configs/armada_38x.h.
Table: NAND Flash Parameters
| Parameter | Description |
|---|---|
CONFIG_ENV_SIZE |
NAND block size in KB: decimal integer in the range 64-16320 (only relevant if boot is from the NAND) |
MV_NAND_PIO_MODE |
NAND uses the I/O mode (use either DMA or I/O mode) |
MV_NAND_1CS_MODE |
1 NAND chip select |
MV_NAND_4BIT_MODE |
ECC mode option (4 bit) |
MTD_NAND_NFC_INIT_RESET |
HW NFC reset |
NOTE: NAND flash parameters must correspond to the actual flash device on board.
The binary header and U-Boot are compiled separately, and combined into one image using the doimage tool.
The doimage options are set in the build.pl file, in the root directory.
The table below lists the image option (img_opt) parameters:
Table: Image Options Parameters for NAND Flash for Boot from NAND
| Parameter | Description |
|---|---|
-L 128 (sample value) |
NAND block size in KB (decimal integer in the range 64-16320) |
-P 2048 (sample value) |
NAND page size (decimal 512, 2048, 4096 or 8192). If the NAND device pages are less than 2 KB, it must be changed to -P 512 |
-N SLC (sample value) |
NAND cell technology type: MLC/SLC |
For example, ARMADA 38x and ARMADA 39x uses the following doimage NAND configuration:
else {
$img_opts = "-P 4096 -L 256 -N SLC";
}
The system configuration is located in file board/mv_ebu/a38x/mvSysHwConfig.h.
The Marvell software package uses predefined flags for adding and removing support for various interfaces and features from the compilation sequence. The following are definitions of units supported by the SoC:
#define MV_INCLUDE_PEX #define MV_INCLUDE_INTEG_SATA #define MV_INCLUDE_GIG_ETH #define MV_INCLUDE_TWSI #define MV_INCLUDE_UART #define MV_INCLUDE_XOR #define MV_INCLUDE_SDIO #define MV_INCLUDE_RTC #define MV_INCLUDE_USB #define MV_INCLUDE_SATA #define MV_INCLUDE_INTEG_SATA#define MV_INCLUDE_TDM #define MV_INCLUDE_SWITCH
To add support for a new PHY, or to modify the initialization sequence, or to alter PHY functionality, such as LED, power up, power down, or interrupt events, add or update the relevant function in: board/mv_ebu/common/mv_hal/eth-phy/mvEthPhy.c.
For example: for the PHY device 88E1116 (0x21), call the function: mvEthE1116PhyBasicInit().
The PHY detection and the call to the above PHY init routine is performed in function mvEthPhyInit(), which is called by mvBoardEgigaPhyInit() (defined in board/mv_ebu/common/USP/mv_phy.c). This only occurs in U-Boot. Other operating systems rely on the U-Boot PHY initialization sequence.
U-Boot uses a small proprietary driver to initialize various NAND devices.
To add support for a new NAND device:
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Add the relevant device information to the MV_NFC_FLASH_INFO structure in the mvNfc.c file located in the board/mv_ebu/common/mv_hal/nfc/ directory.
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Verify that the NAND device ID and other device parameters are defined in drivers/mtd/nand/nand_ids.c.
For example, an MV_NFC_FLASH_INFO entry for the Micron 4 Gbps NAND device:
MV_NFC_FLASH_INFO flashDeviceInfo[] = {
{ /* Micron 4 GB */
.tADL = 70, /* tADL, Address to write data delay */
.tCH = 5, /* tCH, Enable signal hold time */
.tCS = 15, /* tCS, Enable signal setup time */
.tWC = 20, /* tWC, ND_nWE cycle duration */
.tWH = 7, /* tWH, ND_nWE high duration */
.tWP = 10, /* tWP, ND_nWE pulse time */
.tRC = 20, /* tWC, ND_nRE cycle duration */
.tRH = 7, /* tRH, ND_nRE high duration */
.tRP = 10, /* tRP, ND_nRE pulse width */
.tR = 25000, /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read - 25000+20+100+1 */
.tWHR = 60, /* tWHR, ND_nWE high to ND_nRE low delay for status read */
.tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */
.tRHW = 100, /* tRHW, ND_nRE high to ND_nWE low delay */
.pgPrBlk = 64, /* Pages per block - detected */
.pgSz = 2048, /* Page size */
.oobSz = 64, /* Spare size */
.blkNum = 4096, /* Number of blocks/sectors in the flash */
.id = 0xDC2C, /* Device ID 0xDevice,Vendor */
.model = "Micron 4Gb 8bit",
.bb_page = 63, /* Manufacturer Bad block marking page in block */
.flags = NFC_CLOCK_UPSCALE_200M
}