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VIXL Release 1.2
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Refer to the README.md and LICENCE files for details.
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armvixl committed Feb 5, 2014
1 parent 578645f commit f37fdc0
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4 changes: 1 addition & 3 deletions .gitignore
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# ignore python compiled object
*.pyc
# ignore vi temporary files
*.swo
*.swp
.sconsign.dblite
obj/
cctest*
bench_*
libvixl*
example-*
vixl_stats.csv
4 changes: 2 additions & 2 deletions README.md
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VIXL: AArch64 Runtime Code Generation Library Version 1.1
VIXL: AArch64 Runtime Code Generation Library Version 1.2
=========================================================

Contents:
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* No Advanced SIMD support.
* Limited rounding mode support for floating point.
* No support for synchronisation instructions.
* Limited support for synchronisation instructions.
* Limited support for system instructions.
* A few miscellaneous integer and floating point instructions are missing.

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19 changes: 19 additions & 0 deletions doc/changelog.md
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VIXL Change Log
===============

* 1.2
+ Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,
`frinta`, `fcvtau` and `fcvtas`.
+ Added support for assembling and disassembling `isb`, `dsb` and `dmb`.
+ Added support for automatic inversion of compare instructions when using
negative immediates.
+ Added support for using `movn` when generating immediates.
+ Added explicit flag-setting 'S' instructions, and removed
`SetFlags` and `LeaveFlags` arguments.
+ Added support for `Movk` in macro assembler.
+ Added support for W register parameters to `Tbz` and `Tbnz`.
+ Added support for using immediate operands with `Csel`.
+ Added new debugger syntax for memory inspection.
+ Fixed `smull`, `fmsub` and `sdiv` simulation.
+ Fixed sign extension for W->X conversions using `sxtb`, `sxth` and `sxtw`.
+ Prevented code generation for certain side-effect free operations,
such as `add r, r, #0`, in the macro assembler.
+ Other small bug fixes.

* 1.1
+ Improved robustness of instruction decoder and disassembler.
+ Added support for double-to-float conversions using `fcvt`.
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