Merge branch 'KhronosGroup:main' into spv-qcom-image-processing

Kode · Mar 1, 2023 · 2c3cfe2 · 2c3cfe2
2 parents f5fc872 + 295cf5f
commit 2c3cfe2
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Showing 10 changed files with 34 additions and 0 deletions.
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
@@ -193,6 +193,7 @@ namespace Spv
             NumSIMDWorkitemsINTEL = 5896,
             SchedulerTargetFmaxMhzINTEL = 5903,
             StreamingInterfaceINTEL = 6154,
+            RegisterMapInterfaceINTEL = 6160,
             NamedBarrierCountINTEL = 6417,
         }
 
@@ -1152,6 +1153,7 @@ namespace Spv
             AtomicFloat16AddEXT = 6095,
             DebugInfoModuleINTEL = 6114,
             SplitBarrierINTEL = 6141,
+            FPGAKernelAttributesv2INTEL = 6161,
             FPGAArgumentInterfacesINTEL = 6174,
             GroupUniformArithmeticKHR = 6400,
         }

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
@@ -10776,6 +10776,15 @@
           "capabilities" : [ "FPGAKernelAttributesINTEL" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "RegisterMapInterfaceINTEL",
+          "value" : 6160,
+          "parameters" : [
+            { "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" }
+          ],
+          "capabilities" : [ "FPGAKernelAttributesv2INTEL" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "NamedBarrierCountINTEL",
           "value" : 6417,
@@ -14984,6 +14993,13 @@
           "extensions" : [ "SPV_INTEL_split_barrier" ],
           "version" : "None"
         },
+        {
+          "enumerant" : "FPGAKernelAttributesv2INTEL",
+          "value" : 6161,
+          "capabilities" : [ "FPGAKernelAttributesINTEL" ],
+          "extensions" : [ "SPV_INTEL_kernel_attributes" ],
+          "version" : "None"
+        },
         {
           "enumerant" : "FPGAArgumentInterfacesINTEL",
           "value" : 6174,

diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
@@ -192,6 +192,7 @@ public enum ExecutionMode
             NumSIMDWorkitemsINTEL = 5896,
             SchedulerTargetFmaxMhzINTEL = 5903,
             StreamingInterfaceINTEL = 6154,
+            RegisterMapInterfaceINTEL = 6160,
             NamedBarrierCountINTEL = 6417,
         }
 
@@ -1151,6 +1152,7 @@ public enum Capability
             AtomicFloat16AddEXT = 6095,
             DebugInfoModuleINTEL = 6114,
             SplitBarrierINTEL = 6141,
+            FPGAKernelAttributesv2INTEL = 6161,
             FPGAArgumentInterfacesINTEL = 6174,
             GroupUniformArithmeticKHR = 6400,
         }

diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
@@ -200,6 +200,7 @@ typedef enum SpvExecutionMode_ {
     SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
     SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
     SpvExecutionModeStreamingInterfaceINTEL = 6154,
+    SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
     SpvExecutionModeNamedBarrierCountINTEL = 6417,
     SpvExecutionModeMax = 0x7fffffff,
 } SpvExecutionMode;
@@ -1151,6 +1152,7 @@ typedef enum SpvCapability_ {
     SpvCapabilityAtomicFloat16AddEXT = 6095,
     SpvCapabilityDebugInfoModuleINTEL = 6114,
     SpvCapabilitySplitBarrierINTEL = 6141,
+    SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
     SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
     SpvCapabilityGroupUniformArithmeticKHR = 6400,
     SpvCapabilityMax = 0x7fffffff,

diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
@@ -196,6 +196,7 @@ enum ExecutionMode {
     ExecutionModeNumSIMDWorkitemsINTEL = 5896,
     ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
     ExecutionModeStreamingInterfaceINTEL = 6154,
+    ExecutionModeRegisterMapInterfaceINTEL = 6160,
     ExecutionModeNamedBarrierCountINTEL = 6417,
     ExecutionModeMax = 0x7fffffff,
 };
@@ -1147,6 +1148,7 @@ enum Capability {
     CapabilityAtomicFloat16AddEXT = 6095,
     CapabilityDebugInfoModuleINTEL = 6114,
     CapabilitySplitBarrierINTEL = 6141,
+    CapabilityFPGAKernelAttributesv2INTEL = 6161,
     CapabilityFPGAArgumentInterfacesINTEL = 6174,
     CapabilityGroupUniformArithmeticKHR = 6400,
     CapabilityMax = 0x7fffffff,

diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
@@ -196,6 +196,7 @@ enum class ExecutionMode : unsigned {
     NumSIMDWorkitemsINTEL = 5896,
     SchedulerTargetFmaxMhzINTEL = 5903,
     StreamingInterfaceINTEL = 6154,
+    RegisterMapInterfaceINTEL = 6160,
     NamedBarrierCountINTEL = 6417,
     Max = 0x7fffffff,
 };
@@ -1147,6 +1148,7 @@ enum class Capability : unsigned {
     AtomicFloat16AddEXT = 6095,
     DebugInfoModuleINTEL = 6114,
     SplitBarrierINTEL = 6141,
+    FPGAKernelAttributesv2INTEL = 6161,
     FPGAArgumentInterfacesINTEL = 6174,
     GroupUniformArithmeticKHR = 6400,
     Max = 0x7fffffff,

diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
@@ -215,6 +215,7 @@
                     "NumSIMDWorkitemsINTEL": 5896,
                     "SchedulerTargetFmaxMhzINTEL": 5903,
                     "StreamingInterfaceINTEL": 6154,
+                    "RegisterMapInterfaceINTEL": 6160,
                     "NamedBarrierCountINTEL": 6417
                 }
             },
@@ -1127,6 +1128,7 @@
                     "AtomicFloat16AddEXT": 6095,
                     "DebugInfoModuleINTEL": 6114,
                     "SplitBarrierINTEL": 6141,
+                    "FPGAKernelAttributesv2INTEL": 6161,
                     "FPGAArgumentInterfacesINTEL": 6174,
                     "GroupUniformArithmeticKHR": 6400
                 }

diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
@@ -183,6 +183,7 @@ spv = {
         NumSIMDWorkitemsINTEL = 5896,
         SchedulerTargetFmaxMhzINTEL = 5903,
         StreamingInterfaceINTEL = 6154,
+        RegisterMapInterfaceINTEL = 6160,
         NamedBarrierCountINTEL = 6417,
     },
 
@@ -1109,6 +1110,7 @@ spv = {
         AtomicFloat16AddEXT = 6095,
         DebugInfoModuleINTEL = 6114,
         SplitBarrierINTEL = 6141,
+        FPGAKernelAttributesv2INTEL = 6161,
         FPGAArgumentInterfacesINTEL = 6174,
         GroupUniformArithmeticKHR = 6400,
     },

diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
@@ -183,6 +183,7 @@
         'NumSIMDWorkitemsINTEL' : 5896,
         'SchedulerTargetFmaxMhzINTEL' : 5903,
         'StreamingInterfaceINTEL' : 6154,
+        'RegisterMapInterfaceINTEL' : 6160,
         'NamedBarrierCountINTEL' : 6417,
     },
 
@@ -1109,6 +1110,7 @@
         'AtomicFloat16AddEXT' : 6095,
         'DebugInfoModuleINTEL' : 6114,
         'SplitBarrierINTEL' : 6141,
+        'FPGAKernelAttributesv2INTEL' : 6161,
         'FPGAArgumentInterfacesINTEL' : 6174,
         'GroupUniformArithmeticKHR' : 6400,
     },

diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
@@ -195,6 +195,7 @@ enum ExecutionMode : uint
     NumSIMDWorkitemsINTEL = 5896,
     SchedulerTargetFmaxMhzINTEL = 5903,
     StreamingInterfaceINTEL = 6154,
+    RegisterMapInterfaceINTEL = 6160,
     NamedBarrierCountINTEL = 6417,
 }
 
@@ -1154,6 +1155,7 @@ enum Capability : uint
     AtomicFloat16AddEXT = 6095,
     DebugInfoModuleINTEL = 6114,
     SplitBarrierINTEL = 6141,
+    FPGAKernelAttributesv2INTEL = 6161,
     FPGAArgumentInterfacesINTEL = 6174,
     GroupUniformArithmeticKHR = 6400,
 }