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Add vscale_range attribute to functions with sve #58433

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Add vscale_range attribute to functions with sve #58433

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11 changes: 11 additions & 0 deletions src/llvm-cpufeatures.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,17 @@ bool lowerCPUFeatures(Module &M) JL_NOTSAFEPOINT
Materialized.push_back(I);
}
}
if (TT.isAArch64()) {
Attribute FSAttr = F.getFnAttribute("target-features");
StringRef FS =
FSAttr.isValid() ? FSAttr.getValueAsString() : jl_ExecutionEngine->getTargetFeatureString();
SmallVector<StringRef, 128> Features;
FS.split(Features, ',');
for (StringRef Feature : Features) {
if (Feature == "sve")
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Suggested change
if (Feature == "sve")
if (Feature == "+sve")

With this the function gets the attribute vscale_range

; Function Attrs: vscale_range(1,16)
define swiftcc void @"julia_axpy!_763"(ptr nonnull swiftself %pgcstack_arg, double %"a::Float64", ptr noundef nonnull align 8 dereferenceable(24) %"x::Array", ptr noundef nonnull align 8 dereferenceable(24) %"y::Array") local_unnamed_addr #0 !dbg !4 {
; [...]
attributes #0 = { vscale_range(1,16) "frame-pointer"="all" "julia.fsig"="axpy!(Float64, Array{Float64, 1}, Array{Float64, 1})" "probe-stack"="inline-asm" }
attributes #1 = { noinline optnone vscale_range(1,16) "frame-pointer"="all" "probe-stack"="inline-asm" }
attributes #2 = { memory(argmem: readwrite, inaccessiblemem: readwrite) vscale_range(1,16) }
attributes #3 = { mustprogress nofree norecurse nosync nounwind speculatable willreturn memory(none) vscale_range(1,16) }
attributes #4 = { noreturn vscale_range(1,16) "frame-pointer"="all" "julia.fsig"="throw_eachindex_mismatch_indices(String, Base.OneTo{Int64}, Base.OneTo{Int64})" "probe-stack"="inline-asm" }
attributes #5 = { nounwind willreturn allockind("alloc") allocsize(2) memory(argmem: read, inaccessiblemem: readwrite) }
attributes #6 = { memory(argmem: readwrite, inaccessiblemem: readwrite) }
attributes #7 = { nounwind willreturn allockind("alloc") allocsize(1) memory(argmem: read, inaccessiblemem: readwrite) }
attributes #8 = { noreturn }

but there's still not vscale in the vector body.

F.addFnAttr(llvm::Attribute::getWithVScaleRangeArgs(M.getContext(), 1, 16)); //Hardcode for now
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This is relevant for risc-v, too. I've got access to a chip with scalable vector registers (RVV extension), now, if only we could compile julia for that architecture: #57569 😇

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Maybe there's a way to check if the target supports vscale? Is https://github.com/llvm/llvm-project/blob/689a960b693446f0d258240fea0c844b6e685d6e/clang/lib/CodeGen/CodeGenFunction.cpp#L1124-L1130 relevant?

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@gbaraldi gbaraldi May 16, 2025 •
edited
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Don't look at how that function is implemented, you will find something similar :)

}
}
}

if (!Materialized.empty()) {
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