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  1. Scheduller_Memory_Controller Scheduller_Memory_Controller Public

    This is a design for the simulation of the scheduler portion of a memory controller capable serving a 12-core 4.8 GHz processor employing a single 16GB PC5- 38400 DIMM. The system uses a relaxed co…

    SystemVerilog

  2. AHBtoAPB_Formal_Verification AHBtoAPB_Formal_Verification Public

    SystemVerilog

  3. UVM_Verification_FloatingPointUnit UVM_Verification_FloatingPointUnit Public

    SystemVerilog

  4. MIPSlite_5Stage_Pipelined_Simulator MIPSlite_5Stage_Pipelined_Simulator Public

    SystemVerilog

  5. Branch_Prediction Branch_Prediction Public

    C++

  6. Split_L1_Cache Split_L1_Cache Public

    SystemVerilog