Pinned Loading

1. axi_ddr axi_ddr Public

   DDR4 with AXI4 interface RD & WR test

   VHDL 2

2. ddr_bram_interface ddr_bram_interface Public

   SystemVerilog 2

3. DDR4-Naive-WR-RD DDR4-Naive-WR-RD Public

   SystemVerilog 1

4. FM_ADD FM_ADD Public

   SystemVerilog 1

5. ucb-ucie/uciedigital ucb-ucie/uciedigital Public

   Pure digital components of a UCIe controller

   Scala 59 10

6. NPUsim NPUsim Public

   Forked from yonseicasl/NPUsim

   NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators

   C++