We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Educational Computer Architecture Platform
Dockerfile
There was an error while loading. Please reload this page.
⚙️ System-On-Chip implementation integrating ECAP5-DPROC
⚙️ RISC-V softcore for ECAP5
⚙️ Timer peripheral accessible through a Wishbone bus
⚙️ SPI peripheral implementation accessible through a Wishbone bus
⚙️ BRAM memory accessible through a Wishbone bus
⚙️ UART peripheral implementation accessible through a Wishbone bus
⚙️ Wishbone memory-mapped single-cycle interface
🧪 HDL testing libraries for ECAP5
Loading…
