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1. Real-Time-Image-detection-using-ZYBO-Z7 Real-Time-Image-detection-using-ZYBO-Z7 Public

   Verilog

2. soft-core-riscv-cpu soft-core-riscv-cpu Public

   5-stage pipelined RISC-V soft core in Verilog — hazard detection, forwarding, test bench, and implementation on Spartan-7 FPGA .

   Verilog 1

3. home-surveillance-camera home-surveillance-camera Public

   Designing a system which can detect and alert(via email) if any weapons/intruders are detected

   Python