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Pipeline-Verilog
Pipeline-Verilog Public32-bit MIPS32 RISC Processor implemented in Verilog. Features a 5-stage pipeline (IF, ID, EX, MEM, WB) for high-throughput instruction execution. Key Highlights: Supports Arithmetic, Logic, Memory …
Verilog
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Traffic-Light-controller
Traffic-Light-controller PublicThis Verilog module implements a Traffic Light Controller FSM for a highway and country road intersection. It uses five states (S0–S4) to manage signal transitions (Red, Yellow, Green) based on a s…
Verilog
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Snakebite_FirstAid
Snakebite_FirstAid PublicAutomated pneumatic snakebite first-aid for rural India. Delivers WHO-compliant whole-limb compression (50–70 mmHg) via pressure valve — no skill needed. BIA gating detects edema to classify venom …
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Skip_list
Skip_list PublicImplementation-of-Skip-List This repository contains a simple implementation of a Skip List data structure in C++, which supports insertion, deletion, searching, and display operations. Skip Lists …
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