Merge branch 'benesd_feat_terasic_final' into 'devel'

CARDS: [FEATURE] Add Support for Terasic A2700 Accelerator card

See merge request ndk/ndk-fpga!88

apps/minimal/build/a2700/Makefile

@@ -0,0 +1,23 @@
+# Makefile: Makefile for Terasic Mercury A2700 Accelerator Card
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+COMBO_BASE = ../../../..
+CARD_BASE = $(COMBO_BASE)/cards/terasic/a2700
+APP_CONF = app_conf.tcl
+
+
+OUTPUT_NAME = a2700-400g-minimal
+
+all: 400g1
+
+400g1   : ETH_PORT_SPEED=400
+400g1   : ETH_PORT_CHAN=1
+400g1   : OUTPUT_NAME:=$(OUTPUT_NAME)-400g1
+400g1   : EHIP_PORT_TYPE=0
+400g1   : build
+1x400g-8: 400g-1
+
+include $(CARD_BASE)/src/card.mk

apps/minimal/build/a2700/Quartus.tcl

@@ -0,0 +1,31 @@
+# Quartus.tcl: Quartus tcl script to compile whole FPGA design
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: The purpose of this file is described in the Parameterization section of
+# the NDK-CORE documentation.
+
+# ----- Setting basic synthesis options ---------------------------------------
+# NDK & user constants
+source $env(CARD_BASE)/src/Quartus.inc.tcl
+
+# Create only a Quartus project for further design flow driven from Quartus GUI
+# "0" ... full design flow in command line
+# "1" ... project composition only for further dedesign flow in GUI
+set SYNTH_FLAGS(PROJ_ONLY) "0"
+
+# Associative array which is propagated to APPLICATION_CORE, add other
+# parameters if necessary.
+set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE
+
+# Convert associative array to list
+set APP_ARCHGRP_L [array get APP_ARCHGRP]
+
+# ----- Add application core to main component list ---------------------------
+lappend HIERARCHY(COMPONENTS) \
+    [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L]
+
+# Call main function which handle targets
+nb_main

apps/minimal/build/a2700/app_conf.tcl

@@ -0,0 +1,24 @@
+# app_conf.tcl: User parameters for Terasic Mercury A2700 Accelerator Card
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration.
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# The minimum number of RX/TX DMA channels for this card is 32.
+set DMA_RX_CHANNELS      32
+set DMA_TX_CHANNELS      32
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set PROJECT_NAME "NDK_MINIMAL"
+set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS"
+set PROJECT_VERSION [exec cat ../../../../VERSION]

cards/terasic/a2700/config/card_conf.tcl

@@ -0,0 +1,89 @@
+# card_conf.tcl: Default parameters for Terasic A2700
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# NOTE: For the detailed description of this file, visit the Parametrization section
+# in the documentation of the NDK-FPGA/core repository.
+#
+# Mandatory project parameters
+set PROJECT_NAME ""
+
+# ------------------------------------------------------------------------------
+# ETH parameters:
+# ------------------------------------------------------------------------------
+# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED !
+# Note that there are two QSFP ports available, but only 400G is supported.
+set ETH_PORTS          1
+# Speed for each one of the ETH_PORTS (allowed values: 400, 200, 100, 50, 40, 25, 10)
+# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and
+# each index has associated a required port speed.
+# NOTE: at this moment, all ports must have same speed !
+set ETH_PORT_SPEED(0)  $env(ETH_PORT_SPEED)
+# Number of channels for each one of the ETH_PORTS (allowed values: 1, 2, 4, 8)
+# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and
+# each index has associated a required number of channels this port has.
+# NOTE: at this moment, all ports must have same number of channels !
+set ETH_PORT_CHAN(0)   $env(ETH_PORT_CHAN)
+# Number of lanes for each one of the ETH_PORTS
+# Typical values: 4 (QSFP), 8 (QSFP-DD)
+set ETH_PORT_LANES(0)  8
+# EHIP_PORT_TYPE is an array where each index represents given ETH_PORT and
+# each index has associated a required type of IP core, which this port has.
+# NOTE: at this moment, all ports must have same type of IP core !
+set EHIP_PORT_TYPE(0)  $env(EHIP_PORT_TYPE)
+
+# ------------------------------------------------------------------------------
+# PCIe parameters (not all combinations work):
+# ------------------------------------------------------------------------------
+# Supported combinations for this card:
+# 1x PCIe Gen5 x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1
+# 1x PCIe Gen4 x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (Note: limited DMA performance)
+# ------------------------------------------------------------------------------
+
+# Set default PCIe configuration
+set PCIE_CONF "1xGen5x8x8"
+if { [info exist env(PCIE_CONF)] } {
+    set PCIE_CONF $env(PCIE_CONF)
+}
+
+# Parsing PCIE_CONF string to list of parameters
+set pcie_conf_list [ParsePcieConf $PCIE_CONF]
+
+# PCIe Generation (possible values: 4, 5):
+# 4 = PCIe Gen4 (Stratix 10 with P-Tile or Agilex)
+# 5 = PCIe Gen5 (Agilex with R-Tile)
+set PCIE_GEN           [lindex $pcie_conf_list 1]
+# PCIe endpoints (possible values: 2, 4):
+# 2 = 2x PCIe x16 in two slot OR 2x PCIe x8 in one slot (bifurcation x8+x8)
+# 4 = 4x PCIe x8 in two slots (bifurcation x8+x8)
+set PCIE_ENDPOINTS     [lindex $pcie_conf_list 0]
+# PCIe endpoint mode (possible values: 1):
+# 1 = 2x8 lanes (bifurcation x8+x8)
+set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2]
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# This variable can be set in COREs *.mk file or as a parameter when launching the make
+set DMA_TYPE             $env(DMA_TYPE)
+# The minimum number of RX/TX DMA channels for this card is 32.
+set DMA_RX_CHANNELS      32
+set DMA_TX_CHANNELS      32
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# DDR4 parameters:
+# ------------------------------------------------------------------------------
+# Set this parameter to either 0 or 4. Other values are not supported.
+# 0 = Disable SO-DIMM Memory
+# 4 = Use all SO-DIMM modules
+set DDR4_PORTS 4
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set TSU_ENABLE true

cards/terasic/a2700/config/card_const.tcl

@@ -0,0 +1,56 @@
+# card_const.tcl: Card specific parameters for Terasic A2700 (developer only)
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# WARNING: The user should not deliberately change parameters in this file. For
+# the description of this file, visit the Parametrization section in the
+# documentation of the NDK-CORE repostiory
+
+set CARD_NAME "TERASIC-A2700"
+# Achitecture of Clock generator
+set CLOCK_GEN_ARCH "INTEL"
+# Achitecture of PCIe module
+set PCIE_MOD_ARCH "R_TILE"
+# Achitecture of Network module
+set NET_MOD_ARCH "F_TILE"
+# Achitecture of SDM/SYSMON module
+set SDM_SYSMON_ARCH "INTEL_SDM"
+# Boot controller type - SDM
+set BOOT_TYPE 4
+
+# Total number of QSFP cages
+set QSFP_CAGES       1
+# I2C address of each QSFP cage
+set QSFP_I2C_ADDR(0) "0xA0"
+
+# ------------------------------------------------------------------------------
+# Checking of parameter compatibility
+# ------------------------------------------------------------------------------
+
+if {!(($PCIE_ENDPOINTS == 4 && $PCIE_GEN == 4 && $PCIE_ENDPOINT_MODE == 1) ||
+      ($PCIE_ENDPOINTS == 2 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 1) )} {
+    error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
+Allowed PCIe configurations:
+- 2xGen4x8x8 -- PCIE_GEN=4, PCIE_ENDPOINTS=4, PCIE_ENDPOINT_MODE=1
+- 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1"
+}
+
+#DDR4
+if {!($DDR4_PORTS == 0 || $DDR4_PORTS == 4) } {
+    error "Unsupported number of DDR4_PORTS: Select either 0 or 4"
+}
+
+# Enable/add PCIe Gen5 x16 for experiments only!
+#($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 5 && $PCIE_ENDPOINT_MODE == 0) ||
+#- 1xGen5x16  -- PCIE_GEN=5, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0"
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+# Current setup is same for all IP cores, due to use of one pll with frequency (830,156Mhz), for all IP's:
+# This setup value is defined as half of pll frequency
+set TSU_FREQUENCY 415039062
+
+setVhdlPkgInt DDR4_PORTS $DDR4_PORTS

cards/terasic/a2700/constr/device.qsf

@@ -0,0 +1,12 @@
+# device.qsf
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+#  Global assignments
+# ==============================================================================
+
+set_global_assignment -name DEVICE AGIB027R29A1E2VB
+set_global_assignment -name FAMILY Agilex

cards/terasic/a2700/constr/general.qsf

@@ -0,0 +1,68 @@
+# general.qsf
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+#  Global assignments
+# ==============================================================================
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name DEVICE_IO_STANDARD_ALL "1.2 V"
+
+set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
+set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
+set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
+set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 75
+set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE OFF
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
+set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
+
+#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "AVST X8"
+# This is used for boot via SDM
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
+set_global_assignment -name USE_CONF_DONE SDM_IO16
+set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ
+
+# F-Tile XCVR PRESERVE_UNUSED_XCVR_CHANNEL
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
+
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO
+set_global_assignment -name CVP_MODE OFF
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN OFF
+set_global_assignment -name HPS_DAP_SPLIT_MODE DISABLED
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 64
+#set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_115MHZ_IOSC
+set_global_assignment -name GENERATE_COMPRESSED_SOF ON
+
+
+set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
+
+# ==============================================================================
+#  Pinout and IO Standards
+# ==============================================================================
+
+#50MHz
+set_location_assignment PIN_J41 -to AG_SYSCLK1_P
+
+#100MHz - There may be a bug in Quartus that makes it virtually impossible to use this constraint with multiple EMIF controllers.
+#It is possible to use this pin if Quartus assigns it automatically. More information here:
+#https://community.intel.com/t5/Intel-Quartus-Prime-Software/Stratix-10-HPS-DDR4-EMIF-placement-error/m-p/1601633
+#set_location_assignment PIN_LB60 -to AG_SYSCLK1_P
+
+set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK0_P
+set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to AG_SYSCLK1_P
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK0_P
+set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to AG_SYSCLK1_P
+
+
+set_global_assignment -name OCP_HW_EVAL DISABLE
+# this parameter was set as disable because it makes problem with build for ftile IP cores