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jakubcabaljakubcabal
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Merge branch 'benesd_feat_axi_user_signal' into 'devel'
feat(axi2mfb): add tuser signal See merge request ndk/ndk-fpga!186
2 parents e47f2df + 33cf8c5 commit d24d8f9

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10 files changed

+147
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‎comp/mfb_tools/axi/axi2mfb/axi2mfb.vhd‎

Lines changed: 51 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ use IEEE.std_logic_1164.all;
1010
use ieee.numeric_std.all;
1111

1212
use work.math_pack.all;
13+
use work.type_pack.all;
1314

1415
-- -------------------------------------------------------------------------
1516
-- Description
@@ -50,6 +51,16 @@ entity AXI2MFB is
5051
-- AXI stream data width
5152
AXI_DATA_WIDTH : natural := 256;
5253

54+
-- AXI stream metadata width
55+
AXI_USER_WIDTH : natural := 0;
56+
57+
-- The division per regions must be performed afterward
58+
META_WIDTH : natural := AXI_USER_WIDTH;
59+
60+
-- MFB_META_WITH_SOF = true => META signal is aligned with SOF
61+
-- MFB_META_WITH_SOF = false => META signal is aligned with EOF (if EOF is not set, the user is forwarded to region 0)
62+
MFB_META_WITH_SOF : boolean := true;
63+
5364
-- =============================
5465
-- Others (PIPE config)
5566
-- =============================
@@ -70,6 +81,7 @@ entity AXI2MFB is
7081
-- =========================================================================
7182

7283
RX_AXI_TDATA : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
84+
RX_AXI_TUSER : in std_logic_vector(AXI_USER_WIDTH - 1 downto 0) := (others => '0');
7385
RX_AXI_TKEEP : in std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0);
7486
RX_AXI_TLAST : in std_logic;
7587
RX_AXI_TVALID : in std_logic;
@@ -80,6 +92,8 @@ entity AXI2MFB is
8092
-- =========================================================================
8193

8294
TX_MFB_DATA : out std_logic_vector(REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH-1 downto 0);
95+
-- Valid with SOF
96+
TX_MFB_META : out std_logic_vector(REGIONS*META_WIDTH - 1 downto 0);
8397
TX_MFB_SOF_POS : out std_logic_vector(REGIONS*max(1,log2(REGION_SIZE))-1 downto 0);
8498
TX_MFB_EOF_POS : out std_logic_vector(REGIONS*max(1,log2(REGION_SIZE*BLOCK_SIZE))-1 downto 0);
8599
TX_MFB_SOF : out std_logic_vector(REGIONS-1 downto 0);
@@ -111,6 +125,7 @@ architecture behavioral of AXI2MFB is
111125
-- s0 => s1
112126
signal axi_tlast_s1 : std_logic;
113127
signal axi_tdata_s1 : std_logic_vector(RX_AXI_TDATA'RANGE);
128+
signal axi_tuser_s1 : std_logic_vector(RX_AXI_TUSER'RANGE);
114129
signal axi_tkeep_s1 : std_logic_vector(RX_AXI_TKEEP'RANGE);
115130
signal src_rdy_s1 : std_logic;
116131
signal dst_rdy_s1 : std_logic;
@@ -120,6 +135,10 @@ architecture behavioral of AXI2MFB is
120135
signal mfb_sof_s1 : std_logic_vector(TX_MFB_SOF'RANGE);
121136
signal mfb_eof_s1 : std_logic_vector(TX_MFB_EOF'RANGE);
122137

138+
-- Meta signal array
139+
signal mfb_meta_s1 : std_logic_vector(REGIONS*META_WIDTH - 1 downto 0);
140+
signal mfb_meta_arr_s1 : slv_array_t(REGIONS - 1 downto 0)(META_WIDTH - 1 downto 0):= (others => (others => '0'));
141+
123142

124143
begin
125144
-----------------------------------------------------------------------------
@@ -137,12 +156,16 @@ begin
137156
-- 4. MFB and AXI stream data width needs to be equal
138157
assert (MFB_DATA_WIDTH = AXI_DATA_WIDTH) report "AXI2MFB: MFB and AXIs data width is not matching" severity FAILURE;
139158

159+
-- 5. MFB and AXI meta signal must have same width
160+
assert (META_WIDTH = AXI_USER_WIDTH) report "AXI2MFB: MFB and AXIs meta width is not matching" severity FAILURE;
161+
140162
-----------------------------------------------------------------------------
141163
-- input stage (s0 => s1)
142164
-----------------------------------------------------------------------------
143165
input_pipe_i : entity work.AXI_PIPE
144166
generic map(
145167
AXI_DATA_WIDTH => AXI_DATA_WIDTH,
168+
AXI_USER_WIDTH => AXI_USER_WIDTH,
146169
FAKE_PIPE => not USE_IN_PIPE,
147170
USE_DST_RDY => true,
148171
PIPE_TYPE => PIPE_TYPE,
@@ -153,12 +176,14 @@ begin
153176
RESET => RST,
154177

155178
RX_AXI_TDATA => RX_AXI_TDATA,
179+
RX_AXI_TUSER => RX_AXI_TUSER,
156180
RX_AXI_TKEEP => RX_AXI_TKEEP,
157181
RX_AXI_TLAST => RX_AXI_TLAST,
158182
RX_AXI_TVALID => RX_AXI_TVALID,
159183
RX_AXI_TREADY => RX_AXI_TREADY,
160184

161185
TX_AXI_TDATA => axi_tdata_s1,
186+
TX_AXI_TUSER => axi_tuser_s1,
162187
TX_AXI_TKEEP => axi_tkeep_s1,
163188
TX_AXI_TLAST => axi_tlast_s1,
164189
TX_AXI_TVALID => src_rdy_s1,
@@ -190,6 +215,28 @@ begin
190215
-- TX_MFB_SOF is asserted after last packet has ended (start_frame flag)
191216
mfb_sof_s1 <= (0 => frame_start_q, others => '0');
192217

218+
valid_with_what_g : if (MFB_META_WITH_SOF) generate
219+
-- SOF can appear only in region 0
220+
mfb_meta_arr_s1(0) <= axi_tuser_s1;
221+
else generate
222+
-- Find eof region
223+
find_eof_p: process(all)
224+
variable eof_region_int : integer range 0 to max(1, log2(REGIONS+1));
225+
begin
226+
eof_region_int := 0;
227+
mfb_meta_arr_s1 <= (others => (others => '0'));
228+
find_eof_l: for r in 0 to REGIONS - 1 loop
229+
if mfb_eof_s1(r) = '1' then
230+
eof_region_int := r;
231+
exit;
232+
end if;
233+
end loop;
234+
-- place user signal in region where eof is specified
235+
-- if eof is not available, user signal is placed in first region
236+
mfb_meta_arr_s1(eof_region_int) <= axi_tuser_s1;
237+
end process;
238+
end generate;
239+
193240
-- default assignemnt for virtual region
194241
tkeep_split(REGIONS) <= (others => '0');
195242

@@ -220,13 +267,14 @@ begin
220267
-----------------------------------------------------------------------------
221268
-- output stage (s1 => s2)
222269
-----------------------------------------------------------------------------
270+
mfb_meta_s1 <= slv_array_ser(mfb_meta_arr_s1);
223271
output_pipe_i : entity work.MFB_PIPE
224272
generic map(
225273
REGIONS => REGIONS,
226274
REGION_SIZE => REGION_SIZE,
227275
BLOCK_SIZE => BLOCK_SIZE,
228276
ITEM_WIDTH => ITEM_WIDTH,
229-
META_WIDTH => 0,
277+
META_WIDTH => META_WIDTH,
230278

231279
FAKE_PIPE => not USE_OUT_PIPE,
232280
USE_DST_RDY => true,
@@ -238,7 +286,7 @@ begin
238286
RESET => RST,
239287

240288
RX_DATA => axi_tdata_s1,
241-
RX_META => (others => '0'),
289+
RX_META => mfb_meta_s1,
242290
RX_SOF_POS => (others => '0'), -- SOF POS is fixed to 0
243291
RX_EOF_POS => mfb_eof_pos_s1,
244292
RX_SOF => mfb_sof_s1,
@@ -247,7 +295,7 @@ begin
247295
RX_DST_RDY => dst_rdy_s1,
248296

249297
TX_DATA => TX_MFB_DATA,
250-
TX_META => open,
298+
TX_META => TX_MFB_META,
251299
TX_SOF_POS => TX_MFB_SOF_POS,
252300
TX_EOF_POS => TX_MFB_EOF_POS,
253301
TX_SOF => TX_MFB_SOF,

‎comp/mfb_tools/axi/axi2mfb/ver/tbench/dut.sv‎

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -15,26 +15,31 @@ module DUT (
1515
);
1616

1717
AXI2MFB #(
18-
.USE_IN_PIPE (USE_IN_PIPE),
19-
.USE_OUT_PIPE (USE_OUT_PIPE),
20-
.REGIONS (REGIONS),
21-
.REGION_SIZE (REGION_SIZE),
22-
.BLOCK_SIZE (BLOCK_SIZE),
23-
.ITEM_WIDTH (ITEM_WIDTH),
24-
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
25-
.PIPE_TYPE (PIPE_TYPE),
26-
.DEVICE (DEVICE)
18+
.USE_IN_PIPE (USE_IN_PIPE),
19+
.USE_OUT_PIPE (USE_OUT_PIPE),
20+
.REGIONS (REGIONS),
21+
.REGION_SIZE (REGION_SIZE),
22+
.BLOCK_SIZE (BLOCK_SIZE),
23+
.ITEM_WIDTH (ITEM_WIDTH),
24+
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
25+
.AXI_USER_WIDTH (AXI_USER_WIDTH),
26+
.META_WIDTH (META_WIDTH),
27+
.MFB_META_WITH_SOF (!META_ALIGNMENT),
28+
.PIPE_TYPE (PIPE_TYPE),
29+
.DEVICE (DEVICE)
2730
) VHDL_DUT_U (
2831
.CLK (CLK),
2932
.RST (RESET),
3033

3134
.RX_AXI_TDATA (RX.TDATA),
35+
.RX_AXI_TUSER (RX.TUSER),
3236
.RX_AXI_TKEEP (RX.TKEEP),
3337
.RX_AXI_TLAST (RX.TLAST),
3438
.RX_AXI_TVALID (RX.TVALID),
3539
.RX_AXI_TREADY (RX.TREADY),
3640

3741
.TX_MFB_DATA (TX.DATA),
42+
.TX_MFB_META (TX.META),
3843
.TX_MFB_SOF_POS (TX.SOF_POS),
3944
.TX_MFB_EOF_POS (TX.EOF_POS),
4045
.TX_MFB_SOF (TX.SOF),

‎comp/mfb_tools/axi/axi2mfb/ver/tbench/scoreboard.sv‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,15 @@ class ScoreboardDriverCbs extends DriverCbs;
1818
endfunction
1919

2020
virtual task pre_tx(ref Transaction transaction, string inst);
21-
AxiTransaction #(ITEM_WIDTH) t_axi;
22-
MfbTransaction #(ITEM_WIDTH) t_mfb;
21+
AxiTransaction #(ITEM_WIDTH, AXI_USER_WIDTH) t_axi;
22+
MfbTransaction #(ITEM_WIDTH, META_WIDTH) t_mfb;
2323
t_mfb = new;
2424

2525
$cast(t_axi, transaction);
2626
t_mfb.data = t_axi.data;
27+
t_mfb.meta = t_axi.user;
28+
// Enable Meta Signal Comparison
29+
t_mfb.check_meta = 1'b1;
2730

2831
sc_table.add(t_mfb);
2932
endtask

‎comp/mfb_tools/axi/axi2mfb/ver/tbench/test.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,11 @@ program TEST (
1818
iMfbTx.monitor MONITOR
1919
);
2020

21-
AxiTransaction #(ITEM_WIDTH) blueprint;
21+
AxiTransaction #(ITEM_WIDTH, AXI_USER_WIDTH) blueprint;
2222
Generator generator;
23-
Axi4SDriver #(AXI_DATA_WIDTH, META_WIDTH, ITEM_WIDTH) driver;
24-
MfbResponder #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH) responder;
25-
MfbMonitor #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH) monitor;
23+
Axi4SDriver #(AXI_DATA_WIDTH, AXI_USER_WIDTH, ITEM_WIDTH) driver;
24+
MfbResponder #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH,META_WIDTH) responder;
25+
MfbMonitor #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH,META_WIDTH,META_ALIGNMENT) monitor;
2626
Scoreboard scoreboard;
2727

2828

‎comp/mfb_tools/axi/axi2mfb/ver/tbench/test_pkg.sv‎

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,16 +9,20 @@ package test_pkg;
99

1010
import math_pkg::*;
1111

12-
parameter REGIONS = 1;
13-
parameter REGION_SIZE = 4;
14-
parameter BLOCK_SIZE = 8;
15-
parameter ITEM_WIDTH = 8;
16-
parameter META_WIDTH = 0;
17-
parameter USE_IN_PIPE = 0;
18-
parameter USE_OUT_PIPE = 0;
19-
parameter AXI_DATA_WIDTH = REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH;;
20-
parameter PIPE_TYPE = "SHREG";
21-
parameter DEVICE = "7SERIES";
12+
parameter REGIONS = 4;
13+
parameter REGION_SIZE = 4;
14+
parameter BLOCK_SIZE = 8;
15+
parameter ITEM_WIDTH = 8;
16+
parameter USE_IN_PIPE = 0;
17+
parameter USE_OUT_PIPE = 1;
18+
// META_ALIGNMENT=0 => META signal is aligned with SOF,
19+
// META_ALIGNMENT=1 => META signal is aligned with EOF.
20+
parameter META_ALIGNMENT = 0;
21+
parameter AXI_DATA_WIDTH = REGIONS*REGION_SIZE*BLOCK_SIZE*ITEM_WIDTH;
22+
parameter AXI_USER_WIDTH = 32;
23+
parameter META_WIDTH = AXI_USER_WIDTH;
24+
parameter PIPE_TYPE = "SHREG";
25+
parameter DEVICE = "7SERIES";
2226

2327
`include "scoreboard.sv"
2428

‎comp/mfb_tools/axi/axi2mfb/ver/tbench/testbench.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ module testbench;
1111

1212
logic CLK = 0;
1313
logic RESET;
14-
iMfbTx #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH) TX (CLK, RESET);
15-
iAxi4SRx #(AXI_DATA_WIDTH, META_WIDTH, ITEM_WIDTH) RX (CLK, RESET);
14+
iMfbTx #(REGIONS,REGION_SIZE,BLOCK_SIZE,ITEM_WIDTH,META_WIDTH) TX (CLK, RESET);
15+
iAxi4SRx #(AXI_DATA_WIDTH, AXI_USER_WIDTH, ITEM_WIDTH) RX (CLK, RESET);
1616

1717
always #(CLK_PERIOD/2) CLK = ~CLK;
1818

‎comp/mfb_tools/axi/axi2mfb/ver/ver_settings.py‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,10 @@
1111
"BLOCK_SIZE" : "8",
1212
"ITEM_WIDTH" : "8",
1313
"AXI_DATA_WIDTH" : "256",
14+
"AXI_USER_WIDTH" : "32",
1415
"USE_IN_PIPE" : "0",
1516
"USE_OUT_PIPE" : "0",
17+
"META_ALIGNMENT" : "0",
1618
},
1719
"region_comb_1" : {
1820
"REGIONS" : "1",
@@ -55,17 +57,29 @@
5557
"pipe_out" : {
5658
"USE_OUT_PIPE" : "1",
5759
},
60+
"meta_sof" : {
61+
"META_ALIGNMENT" : "0",
62+
},
63+
"meta_eof" : {
64+
"META_ALIGNMENT" : "1",
65+
},
66+
"user_1bit" : {
67+
"AXI_USER_WIDTH" : "1",
68+
},
5869
"_combinations_" : (
5970
(), # Works the same as '("default",),' as the "default" is applied in every combination
6071
("pipe_in",),
6172
("pipe_out",),
6273
("pipe_in","pipe_out",),
6374

6475
("region_comb_1",),
76+
("region_comb_1", "user_1bit",),
6577
("region_comb_2",),
6678
("region_comb_3",),
6779
("region_comb_4",),
68-
("region_comb_5",),
80+
("region_comb_5", "meta_sof",),
81+
("region_comb_5", "meta_eof",),
82+
("region_comb_5", "user_1bit",),
6983
("region_comb_5","pipe_in","pipe_out",),
7084

7185
),

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