Merge branch 'kondys_fix_tsdemo_inf_widths' into 'devel'

fix: adjust width of signals/ports for TS Demo

See merge request ndk/ndk-fpga!188

Author: jakubcabal

core/comp/app/application_ent.vhd

@@ -239,7 +239,7 @@ port (
 
     -- This interface is to transmit Channel IDs and Timestamps of packets
     -- from the APP Core to the demo/testing logic in the Network Mod Core (E-Tile).
-    ETH_TX_MVB_CHANNEL      : out std_logic_vector(ETH_STREAMS* MFB_REGIONS*log2(DMA_TX_CHANNELS)-1 downto 0);
+    ETH_TX_MVB_CHANNEL      : out std_logic_vector(ETH_STREAMS* MFB_REGIONS*log2(DMA_TX_CHANNELS/(ETH_STREAMS/DMA_STREAMS))-1 downto 0);
     ETH_TX_MVB_TIMESTAMP    : out std_logic_vector(ETH_STREAMS* MFB_REGIONS*48-1 downto 0);
     ETH_TX_MVB_VLD          : out std_logic_vector(ETH_STREAMS* MFB_REGIONS-1 downto 0) := (others => '0');
 

core/comp/eth/network_mod/network_mod_ent.vhd

@@ -80,6 +80,7 @@ generic(
     -- The measured data is presented to the user via a couple of dedicated registers.
     -- WARNING: works only for a single-channel (and single-Region) designs with E-Tile (Intel)!
     TS_DEMO_EN        : boolean := false;
+    -- TX_DMA_CHANNELS per Eth Stream!
     TX_DMA_CHANNELS   : natural := 16;
     -- Enable low latency optimalization
     LL_MODE           : boolean := false;

core/top/fpga_common.vhd

@@ -639,7 +639,7 @@ architecture FULL of FPGA_COMMON is
     signal eth_tx_mfb_src_rdy            : std_logic_vector(ETH_STREAMS-1 downto 0);
     signal eth_tx_mfb_dst_rdy            : std_logic_vector(ETH_STREAMS-1 downto 0) := (others => '1');
 
-    signal eth_tx_mvb_channel            : std_logic_vector(ETH_STREAMS*ETH_MFB_REGIONS*log2(DMA_TX_CHANNELS)-1 downto 0);
+    signal eth_tx_mvb_channel            : std_logic_vector(ETH_STREAMS*ETH_MFB_REGIONS*log2(DMA_TX_CHANNELS/(ETH_STREAMS/DMA_STREAMS))-1 downto 0);
     signal eth_tx_mvb_timestamp_vld      : std_logic_vector(ETH_STREAMS*ETH_MFB_REGIONS*48-1 downto 0);
     signal eth_tx_mvb_vld                : std_logic_vector(ETH_STREAMS*ETH_MFB_REGIONS-1 downto 0);
 
@@ -1591,7 +1591,7 @@ begin
 
         LL_MODE           => LL_MODE        ,
         TS_DEMO_EN        => TS_DEMO_EN     ,
-        TX_DMA_CHANNELS   => DMA_TX_CHANNELS,
+        TX_DMA_CHANNELS   => DMA_TX_CHANNELS/(ETH_STREAMS/DMA_STREAMS),
 
         LANE_RX_POLARITY  => ETH_LANE_RXPOLARITY,
         LANE_TX_POLARITY  => ETH_LANE_TXPOLARITY,