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jakubcabaljakubcabal
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Merge branch 'cabal_misc_new' into 'devel'
feat: Add MISC signals between Top-Level and APP/PCIE/NET core See merge request ndk/ndk-fpga!97
2 parents d9a8476 + 31f6f41 commit abcb471

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7 files changed

+126
-11
lines changed

7 files changed

+126
-11
lines changed

‎core/comp/app/application_ent.vhd

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,6 +95,10 @@ generic (
9595
FPGA_ID_WIDTH : natural := 64;
9696
-- Width of reset signals
9797
RESET_WIDTH : integer := 2;
98+
-- Width of MISC signal between Top-Level FPGA design and APP core logic
99+
MISC_TOP2APP_WIDTH : natural := 1;
100+
-- Width of MISC signal between APP core logic and Top-Level FPGA design
101+
MISC_APP2TOP_WIDTH : natural := 1;
98102
-- Name of FPGA board
99103
BOARD : string;
100104
-- Name of FPGA device
@@ -433,6 +437,14 @@ port (
433437
-- MI bus: data from slave to master (read data)
434438
MI_DRD : out std_logic_vector(MI_DATA_WIDTH-1 downto 0);
435439
-- MI bus: valid of MI_DRD data signal
436-
MI_DRDY : out std_logic
440+
MI_DRDY : out std_logic;
441+
442+
-- =========================================================================
443+
-- MISC SIGNALS (the clock signal is not defined)
444+
-- =========================================================================
445+
-- Optional signal for MISC connection from Top-Level FPGA design to APP core.
446+
MISC_TOP2APP : in std_logic_vector(MISC_TOP2APP_WIDTH-1 downto 0);
447+
-- Optional signal for MISC connection from APP core to Top-Level FPGA design.
448+
MISC_APP2TOP : out std_logic_vector(MISC_APP2TOP_WIDTH-1 downto 0) := (others => '0')
437449
);
438450
end entity;

‎core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,10 @@ generic(
6666
-- Ethernet lanes polarity
6767
LANE_RX_POLARITY : std_logic_vector(LANES-1 downto 0) := (others => '0');
6868
LANE_TX_POLARITY : std_logic_vector(LANES-1 downto 0) := (others => '0');
69+
-- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
70+
MISC_TOP2NET_WIDTH : natural := 1;
71+
-- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
72+
MISC_NET2TOP_WIDTH : natural := 1;
6973
-- Select correct FPGA device.
7074
-- "AGILEX", "STRATIX10", "ULTRASCALE", ...
7175
DEVICE : string := "STRATIX10"
@@ -138,6 +142,14 @@ port(
138142
MI_BE_PHY : in std_logic_vector(MI_DATA_WIDTH_PHY/8-1 downto 0);
139143
MI_DRD_PHY : out std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0);
140144
MI_ARDY_PHY : out std_logic;
141-
MI_DRDY_PHY : out std_logic
145+
MI_DRDY_PHY : out std_logic;
146+
147+
-- =========================================================================
148+
-- MISC SIGNALS (the clock signal is not defined)
149+
-- =========================================================================
150+
-- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
151+
MISC_TOP2NET : in std_logic_vector(MISC_TOP2NET_WIDTH-1 downto 0);
152+
-- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
153+
MISC_NET2TOP : out std_logic_vector(MISC_NET2TOP_WIDTH-1 downto 0) := (others => '0')
142154
);
143155
end entity;

‎core/comp/eth/network_mod/network_mod.vhd

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -445,6 +445,8 @@ begin
445445
TX_DMA_CHANNELS => TX_DMA_CHANNELS ,
446446
LANE_RX_POLARITY => LANE_RX_POLARITY(p*LANES+LANES-1 downto p*LANES),
447447
LANE_TX_POLARITY => LANE_TX_POLARITY(p*LANES+LANES-1 downto p*LANES),
448+
MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
449+
MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
448450
DEVICE => DEVICE
449451
)
450452
port map (
@@ -499,7 +501,10 @@ begin
499501
MI_WR_PHY => mi_split_wr_phy (p),
500502
MI_DRD_PHY => mi_split_drd_phy (p),
501503
MI_ARDY_PHY => mi_split_ardy_phy(p),
502-
MI_DRDY_PHY => mi_split_drdy_phy(p)
504+
MI_DRDY_PHY => mi_split_drdy_phy(p),
505+
506+
MISC_TOP2NET => MISC_TOP2NET(p),
507+
MISC_NET2TOP => MISC_NET2TOP(p)
503508
);
504509

505510
-- =====================================================================

‎core/comp/eth/network_mod/network_mod_ent.vhd

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,10 @@ generic(
8686
LANE_TX_POLARITY : std_logic_vector(ETH_PORTS*LANES-1 downto 0) := (others => '0');
8787
-- Number of user resets.
8888
RESET_WIDTH : natural := 8;
89+
-- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
90+
MISC_TOP2NET_WIDTH : natural := 1;
91+
-- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
92+
MISC_NET2TOP_WIDTH : natural := 1;
8993
-- Select correct FPGA device.
9094
DEVICE : string := "STRATIX10"; -- AGILEX, STRATIX10, ULTRASCALE
9195
BOARD : string := "DK-DEV-1SDX-P" -- 400G1, DK-DEV-AGI027RES, DK-DEV-1SDX-P
@@ -220,6 +224,14 @@ port(
220224
TSU_CLK : out std_logic;
221225
TSU_RST : out std_logic;
222226
TSU_TS_NS : in std_logic_vector(64-1 downto 0);
223-
TSU_TS_DV : in std_logic
227+
TSU_TS_DV : in std_logic;
228+
229+
-- =========================================================================
230+
-- MISC SIGNALS (the clock signal is not defined)
231+
-- =========================================================================
232+
-- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
233+
MISC_TOP2NET : in slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
234+
-- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
235+
MISC_NET2TOP : out slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0)
224236
);
225237
end entity;

‎core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,10 @@ entity PCIE_CORE is
6161
CARD_ID_WIDTH : natural := 0;
6262
-- Reset width for effective reset duplication
6363
RESET_WIDTH : natural := 8;
64+
-- Width of MISC signal between Top-Level FPGA design and PCIE core logic
65+
MISC_TOP2PCIE_WIDTH : natural := 1;
66+
-- Width of MISC signal between PCIE core logic and Top-Level FPGA design
67+
MISC_PCIE2TOP_WIDTH : natural := 1;
6468
-- FPGA device
6569
DEVICE : string := "STRATIX10"
6670
);
@@ -196,6 +200,14 @@ entity PCIE_CORE is
196200
MI_WR : in std_logic;
197201
MI_DRD : out std_logic_vector(MI_WIDTH-1 downto 0);
198202
MI_ARDY : out std_logic;
199-
MI_DRDY : out std_logic
203+
MI_DRDY : out std_logic;
204+
205+
-- =========================================================================
206+
-- MISC SIGNALS (the clock signal is not defined)
207+
-- =========================================================================
208+
-- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
209+
MISC_TOP2PCIE : in slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0);
210+
-- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
211+
MISC_PCIE2TOP : out slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0) := (others => (others => '0'))
200212
);
201213
end entity;

‎core/comp/pcie/pcie_mod/pcie_top.vhd

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,10 @@ entity PCIE is
7272
DMA_BAR_ENABLE : boolean := false;
7373
-- Enable of XCV IP, for Xilinx only
7474
XVC_ENABLE : boolean := false;
75+
-- Width of MISC signal between Top-Level FPGA design and PCIE core logic
76+
MISC_TOP2PCIE_WIDTH : natural := 1;
77+
-- Width of MISC signal between PCIE core logic and Top-Level FPGA design
78+
MISC_PCIE2TOP_WIDTH : natural := 1;
7579
-- FPGA device
7680
DEVICE : string := "STRATIX10"
7781
);
@@ -230,7 +234,15 @@ entity PCIE is
230234
MI_DBG_WR : in std_logic;
231235
MI_DBG_DRD : out std_logic_vector(32-1 downto 0);
232236
MI_DBG_ARDY : out std_logic;
233-
MI_DBG_DRDY : out std_logic
237+
MI_DBG_DRDY : out std_logic;
238+
239+
-- =====================================================================
240+
-- MISC SIGNALS (the clock signal is not defined)
241+
-- =====================================================================
242+
-- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
243+
MISC_TOP2PCIE : in slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0) := (others => (others => '0'));
244+
-- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
245+
MISC_PCIE2TOP : out slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0)
234246
);
235247
end entity;
236248

@@ -378,6 +390,8 @@ begin
378390
XVC_ENABLE => XVC_ENABLE,
379391
CARD_ID_WIDTH => CARD_ID_WIDTH,
380392
RESET_WIDTH => RESET_WIDTH,
393+
MISC_TOP2PCIE_WIDTH => MISC_TOP2PCIE_WIDTH,
394+
MISC_PCIE2TOP_WIDTH => MISC_PCIE2TOP_WIDTH,
381395
DEVICE => DEVICE
382396
)
383397
port map (
@@ -451,7 +465,10 @@ begin
451465
MI_WR => mi_dbg_split_wr (0),
452466
MI_DRD => mi_dbg_split_drd (0),
453467
MI_ARDY => mi_dbg_split_ardy(0),
454-
MI_DRDY => mi_dbg_split_drdy(0)
468+
MI_DRDY => mi_dbg_split_drdy(0),
469+
470+
MISC_TOP2PCIE => MISC_TOP2PCIE,
471+
MISC_PCIE2TOP => MISC_PCIE2TOP
455472
);
456473

457474
PCIE_USER_CLK <= pcie_clk;

‎core/top/fpga_common.vhd

Lines changed: 49 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -108,8 +108,22 @@ generic (
108108
AMM_FREQ_KHZ : natural := 0;
109109

110110
STATUS_LEDS : natural := 2;
111+
-- Width of MISC signal between Top-Level FPGA design and FPGA_COMMON
111112
MISC_IN_WIDTH : natural := 0;
113+
-- Width of MISC signal between FPGA_COMMON and Top-Level FPGA design
112114
MISC_OUT_WIDTH : natural := 0;
115+
-- Width of MISC signal between Top-Level FPGA design and APP core logic
116+
MISC_TOP2APP_WIDTH : natural := 1;
117+
-- Width of MISC signal between APP core logic and Top-Level FPGA design
118+
MISC_APP2TOP_WIDTH : natural := 1;
119+
-- Width of MISC signal between Top-Level FPGA design and PCIE core logic
120+
MISC_TOP2PCIE_WIDTH : natural := 1;
121+
-- Width of MISC signal between PCIE core logic and Top-Level FPGA design
122+
MISC_PCIE2TOP_WIDTH : natural := 1;
123+
-- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
124+
MISC_TOP2NET_WIDTH : natural := 1;
125+
-- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
126+
MISC_NET2TOP_WIDTH : natural := 1;
113127

114128
DEVICE : string := "AGILEX";
115129
BOARD : string := "400G1"
@@ -244,8 +258,24 @@ port (
244258
BOOT_MI_ARDY : in std_logic := '0';
245259
BOOT_MI_DRDY : in std_logic := '0';
246260

247-
-- Misc interface, board specific
261+
-- =========================================================================
262+
-- MISC SIGNALS (the clock signal is not defined)
263+
-- =========================================================================
264+
-- Optional signal for MISC connection from Top-Level FPGA design to APP core.
265+
MISC_TOP2APP : in std_logic_vector(MISC_TOP2APP_WIDTH-1 downto 0) := (others => '0');
266+
-- Optional signal for MISC connection from APP core to Top-Level FPGA design.
267+
MISC_APP2TOP : out std_logic_vector(MISC_APP2TOP_WIDTH-1 downto 0);
268+
-- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
269+
MISC_TOP2PCIE : in slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0) := (others => (others => '0'));
270+
-- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
271+
MISC_PCIE2TOP : out slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0);
272+
-- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
273+
MISC_TOP2NET : in slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
274+
-- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
275+
MISC_NET2TOP : out slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0);
276+
-- Optional signal for MISC connection from Top-Level FPGA design to FPGA_COMMON.
248277
MISC_IN : in std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0');
278+
-- Optional signal for MISC connection from FPGA_COMMON to Top-Level FPGA design.
249279
MISC_OUT : out std_logic_vector(MISC_OUT_WIDTH-1 downto 0)
250280
);
251281
end entity;
@@ -796,6 +826,8 @@ begin
796826
DMA_BAR_ENABLE => (DMA_TYPE = 4),
797827
XVC_ENABLE => VIRTUAL_DEBUG_ENABLE,
798828
CARD_ID_WIDTH => FPGA_ID_WIDTH,
829+
MISC_TOP2PCIE_WIDTH => MISC_TOP2PCIE_WIDTH,
830+
MISC_PCIE2TOP_WIDTH => MISC_PCIE2TOP_WIDTH,
799831
DEVICE => DEVICE
800832
)
801833
port map (
@@ -881,7 +913,10 @@ begin
881913
MI_DBG_WR => mi_adc_wr (MI_ADC_PORT_PCI_DBG),
882914
MI_DBG_DRD => mi_adc_drd (MI_ADC_PORT_PCI_DBG),
883915
MI_DBG_ARDY => mi_adc_ardy(MI_ADC_PORT_PCI_DBG),
884-
MI_DBG_DRDY => mi_adc_drdy(MI_ADC_PORT_PCI_DBG)
916+
MI_DBG_DRDY => mi_adc_drdy(MI_ADC_PORT_PCI_DBG),
917+
918+
MISC_TOP2PCIE => MISC_TOP2PCIE,
919+
MISC_PCIE2TOP => MISC_PCIE2TOP
885920
);
886921

887922
cdc_pcie_up_g: for i in 0 to PCIE_ENDPOINTS-1 generate
@@ -1293,6 +1328,8 @@ begin
12931328
MI_ADDR_WIDTH => MI_ADDR_WIDTH,
12941329
FPGA_ID_WIDTH => FPGA_ID_WIDTH,
12951330
RESET_WIDTH => RESET_WIDTH,
1331+
MISC_TOP2APP_WIDTH => MISC_TOP2APP_WIDTH,
1332+
MISC_APP2TOP_WIDTH => MISC_APP2TOP_WIDTH,
12961333
BOARD => BOARD,
12971334
DEVICE => DEVICE
12981335
)
@@ -1466,7 +1503,10 @@ begin
14661503
MI_WR => mi_adc_wr(MI_ADC_PORT_USERAPP),
14671504
MI_DRD => mi_adc_drd(MI_ADC_PORT_USERAPP),
14681505
MI_ARDY => mi_adc_ardy(MI_ADC_PORT_USERAPP),
1469-
MI_DRDY => mi_adc_drdy(MI_ADC_PORT_USERAPP)
1506+
MI_DRDY => mi_adc_drdy(MI_ADC_PORT_USERAPP),
1507+
1508+
MISC_TOP2APP => MISC_TOP2APP,
1509+
MISC_APP2TOP => MISC_APP2TOP
14701510
);
14711511

14721512
-- =========================================================================
@@ -1505,6 +1545,8 @@ begin
15051545
LANE_RX_POLARITY => ETH_LANE_RXPOLARITY,
15061546
LANE_TX_POLARITY => ETH_LANE_TXPOLARITY,
15071547
RESET_WIDTH => 1 ,
1548+
MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
1549+
MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
15081550
DEVICE => DEVICE ,
15091551
BOARD => BOARD ,
15101552

@@ -1606,7 +1648,10 @@ begin
16061648
TSU_CLK => tsu_clk,
16071649
TSU_RST => tsu_rst,
16081650
TSU_TS_NS => tsu_ns,
1609-
TSU_TS_DV => tsu_dv
1651+
TSU_TS_DV => tsu_dv,
1652+
1653+
MISC_TOP2NET => MISC_TOP2NET,
1654+
MISC_NET2TOP => MISC_NET2TOP
16101655
);
16111656

16121657
eth_led_ctrl_i: entity work.ETH_LED_CTRL_TOP

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