Merge branch 'cabal_misc_new' into 'devel'

feat: Add MISC signals between Top-Level and APP/PCIE/NET core

See merge request ndk/ndk-fpga!97

core/comp/app/application_ent.vhd

@@ -95,6 +95,10 @@ generic (
     FPGA_ID_WIDTH      : natural := 64;
     -- Width of reset signals
     RESET_WIDTH        : integer := 2;
+    -- Width of MISC signal between Top-Level FPGA design and APP core logic
+    MISC_TOP2APP_WIDTH : natural := 1;
+    -- Width of MISC signal between APP core logic and Top-Level FPGA design
+    MISC_APP2TOP_WIDTH : natural := 1;
     -- Name of FPGA board
     BOARD              : string;
     -- Name of FPGA device
@@ -433,6 +437,14 @@ port (
     -- MI bus: data from slave to master (read data)
     MI_DRD                  : out std_logic_vector(MI_DATA_WIDTH-1 downto 0);
     -- MI bus: valid of MI_DRD data signal
-    MI_DRDY                 : out std_logic
+    MI_DRDY                 : out std_logic;
+
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to APP core.
+    MISC_TOP2APP            : in  std_logic_vector(MISC_TOP2APP_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from APP core to Top-Level FPGA design.
+    MISC_APP2TOP            : out std_logic_vector(MISC_APP2TOP_WIDTH-1 downto 0) := (others => '0')
 );
 end entity;

core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd

@@ -66,6 +66,10 @@ generic(
     -- Ethernet lanes polarity
     LANE_RX_POLARITY  : std_logic_vector(LANES-1 downto 0) := (others => '0');
     LANE_TX_POLARITY  : std_logic_vector(LANES-1 downto 0) := (others => '0');
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH : natural := 1;
     -- Select correct FPGA device.
     -- "AGILEX", "STRATIX10", "ULTRASCALE", ...
     DEVICE            : string  := "STRATIX10"
@@ -138,6 +142,14 @@ port(
     MI_BE_PHY       : in  std_logic_vector(MI_DATA_WIDTH_PHY/8-1 downto 0);
     MI_DRD_PHY      : out std_logic_vector(MI_DATA_WIDTH_PHY-1 downto 0);
     MI_ARDY_PHY     : out std_logic;
-    MI_DRDY_PHY     : out std_logic
+    MI_DRDY_PHY     : out std_logic;
+
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET    : in  std_logic_vector(MISC_TOP2NET_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP    : out std_logic_vector(MISC_NET2TOP_WIDTH-1 downto 0) := (others => '0')
 );
 end entity;

core/comp/eth/network_mod/network_mod.vhd

@@ -445,6 +445,8 @@ begin
             TX_DMA_CHANNELS   => TX_DMA_CHANNELS  ,
             LANE_RX_POLARITY  => LANE_RX_POLARITY(p*LANES+LANES-1 downto p*LANES),
             LANE_TX_POLARITY  => LANE_TX_POLARITY(p*LANES+LANES-1 downto p*LANES),
+            MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
+            MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
             DEVICE            => DEVICE
         )
         port map (
@@ -499,7 +501,10 @@ begin
             MI_WR_PHY       => mi_split_wr_phy  (p),
             MI_DRD_PHY      => mi_split_drd_phy (p),
             MI_ARDY_PHY     => mi_split_ardy_phy(p),
-            MI_DRDY_PHY     => mi_split_drdy_phy(p)
+            MI_DRDY_PHY     => mi_split_drdy_phy(p),
+
+            MISC_TOP2NET    => MISC_TOP2NET(p),
+            MISC_NET2TOP    => MISC_NET2TOP(p)
         );
 
         -- =====================================================================

core/comp/eth/network_mod/network_mod_ent.vhd

@@ -86,6 +86,10 @@ generic(
     LANE_TX_POLARITY  : std_logic_vector(ETH_PORTS*LANES-1 downto 0) := (others => '0');
     -- Number of user resets.
     RESET_WIDTH       : natural := 8;
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH : natural := 1;
     -- Select correct FPGA device.
     DEVICE            : string := "STRATIX10"; -- AGILEX, STRATIX10, ULTRASCALE
     BOARD             : string := "DK-DEV-1SDX-P" -- 400G1, DK-DEV-AGI027RES, DK-DEV-1SDX-P
@@ -220,6 +224,14 @@ port(
     TSU_CLK         : out std_logic;
     TSU_RST         : out std_logic;
     TSU_TS_NS       : in  std_logic_vector(64-1 downto 0);
-    TSU_TS_DV       : in  std_logic
+    TSU_TS_DV       : in  std_logic;
+
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET    : in  slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP    : out slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0)
 );
 end entity;

core/comp/pcie/pcie_mod/comp/pcie_core/pcie_core_ent.vhd

@@ -61,6 +61,10 @@ entity PCIE_CORE is
         CARD_ID_WIDTH    : natural := 0;
         -- Reset width for effective reset duplication
         RESET_WIDTH      : natural := 8;
+        -- Width of MISC signal between Top-Level FPGA design and PCIE core logic
+        MISC_TOP2PCIE_WIDTH : natural := 1;
+        -- Width of MISC signal between PCIE core logic and Top-Level FPGA design
+        MISC_PCIE2TOP_WIDTH : natural := 1;
         -- FPGA device
         DEVICE           : string  := "STRATIX10"
     );
@@ -196,6 +200,14 @@ entity PCIE_CORE is
         MI_WR              : in  std_logic;
         MI_DRD             : out std_logic_vector(MI_WIDTH-1 downto 0);
         MI_ARDY            : out std_logic;
-        MI_DRDY            : out std_logic
+        MI_DRDY            : out std_logic;
+
+        -- =========================================================================
+        -- MISC SIGNALS (the clock signal is not defined)
+        -- =========================================================================
+        -- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
+        MISC_TOP2PCIE      : in  slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0);
+        -- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
+        MISC_PCIE2TOP      : out slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0) := (others => (others => '0'))
     );
 end entity;

core/comp/pcie/pcie_mod/pcie_top.vhd

@@ -72,6 +72,10 @@ entity PCIE is
         DMA_BAR_ENABLE     : boolean := false;
         -- Enable of XCV IP, for Xilinx only
         XVC_ENABLE         : boolean := false;
+        -- Width of MISC signal between Top-Level FPGA design and PCIE core logic
+        MISC_TOP2PCIE_WIDTH : natural := 1;
+        -- Width of MISC signal between PCIE core logic and Top-Level FPGA design
+        MISC_PCIE2TOP_WIDTH : natural := 1;
         -- FPGA device
         DEVICE             : string  := "STRATIX10"
     );
@@ -230,7 +234,15 @@ entity PCIE is
         MI_DBG_WR           : in  std_logic;
         MI_DBG_DRD          : out std_logic_vector(32-1 downto 0);
         MI_DBG_ARDY         : out std_logic;
-        MI_DBG_DRDY         : out std_logic
+        MI_DBG_DRDY         : out std_logic;
+
+        -- =====================================================================
+        -- MISC SIGNALS (the clock signal is not defined)
+        -- =====================================================================
+        -- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
+        MISC_TOP2PCIE      : in  slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0) := (others => (others => '0'));
+        -- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
+        MISC_PCIE2TOP      : out slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0)
     );
 end entity;
 
@@ -378,6 +390,8 @@ begin
         XVC_ENABLE         => XVC_ENABLE,
         CARD_ID_WIDTH      => CARD_ID_WIDTH,
         RESET_WIDTH        => RESET_WIDTH,
+        MISC_TOP2PCIE_WIDTH => MISC_TOP2PCIE_WIDTH,
+        MISC_PCIE2TOP_WIDTH => MISC_PCIE2TOP_WIDTH,
         DEVICE             => DEVICE
     )
     port map (
@@ -451,7 +465,10 @@ begin
         MI_WR               => mi_dbg_split_wr  (0),
         MI_DRD              => mi_dbg_split_drd (0),
         MI_ARDY             => mi_dbg_split_ardy(0),
-        MI_DRDY             => mi_dbg_split_drdy(0)
+        MI_DRDY             => mi_dbg_split_drdy(0),
+
+        MISC_TOP2PCIE       => MISC_TOP2PCIE,
+        MISC_PCIE2TOP       => MISC_PCIE2TOP
     );
 
     PCIE_USER_CLK <= pcie_clk;

core/top/fpga_common.vhd

@@ -108,8 +108,22 @@ generic (
     AMM_FREQ_KHZ            : natural := 0;
 
     STATUS_LEDS             : natural := 2;
+    -- Width of MISC signal between Top-Level FPGA design and FPGA_COMMON
     MISC_IN_WIDTH           : natural := 0;
+    -- Width of MISC signal between FPGA_COMMON and Top-Level FPGA design
     MISC_OUT_WIDTH          : natural := 0;
+    -- Width of MISC signal between Top-Level FPGA design and APP core logic
+    MISC_TOP2APP_WIDTH      : natural := 1;
+    -- Width of MISC signal between APP core logic and Top-Level FPGA design
+    MISC_APP2TOP_WIDTH      : natural := 1;
+    -- Width of MISC signal between Top-Level FPGA design and PCIE core logic
+    MISC_TOP2PCIE_WIDTH     : natural := 1;
+    -- Width of MISC signal between PCIE core logic and Top-Level FPGA design
+    MISC_PCIE2TOP_WIDTH     : natural := 1;
+    -- Width of MISC signal between Top-Level FPGA design and NET_MOD core logic
+    MISC_TOP2NET_WIDTH      : natural := 1;
+    -- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
+    MISC_NET2TOP_WIDTH      : natural := 1;
 
     DEVICE                  : string := "AGILEX";
     BOARD                   : string := "400G1"
@@ -244,8 +258,24 @@ port (
     BOOT_MI_ARDY            : in  std_logic := '0';
     BOOT_MI_DRDY            : in  std_logic := '0';
 
-    -- Misc interface, board specific
+    -- =========================================================================
+    -- MISC SIGNALS (the clock signal is not defined)
+    -- =========================================================================
+    -- Optional signal for MISC connection from Top-Level FPGA design to APP core.
+    MISC_TOP2APP            : in    std_logic_vector(MISC_TOP2APP_WIDTH-1 downto 0) := (others => '0');
+    -- Optional signal for MISC connection from APP core to Top-Level FPGA design.
+    MISC_APP2TOP            : out   std_logic_vector(MISC_APP2TOP_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from Top-Level FPGA design to PCIE core.
+    MISC_TOP2PCIE           : in    slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_TOP2PCIE_WIDTH-1 downto 0) := (others => (others => '0'));
+    -- Optional signal for MISC connection from PCIE core to Top-Level FPGA design.
+    MISC_PCIE2TOP           : out   slv_array_t(PCIE_ENDPOINTS-1 downto 0)(MISC_PCIE2TOP_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from Top-Level FPGA design to NET_MOD core.
+    MISC_TOP2NET            : in    slv_array_t(ETH_PORTS-1 downto 0)(MISC_TOP2NET_WIDTH-1 downto 0) := (others => (others => '0'));
+    -- Optional signal for MISC connection from NET_MOD core to Top-Level FPGA design.
+    MISC_NET2TOP            : out   slv_array_t(ETH_PORTS-1 downto 0)(MISC_NET2TOP_WIDTH-1 downto 0);
+    -- Optional signal for MISC connection from Top-Level FPGA design to FPGA_COMMON.
     MISC_IN                 : in    std_logic_vector(MISC_IN_WIDTH-1 downto 0) := (others => '0');
+    -- Optional signal for MISC connection from FPGA_COMMON to Top-Level FPGA design.
     MISC_OUT                : out   std_logic_vector(MISC_OUT_WIDTH-1 downto 0)
 );
 end entity;
@@ -796,6 +826,8 @@ begin
         DMA_BAR_ENABLE      => (DMA_TYPE = 4),
         XVC_ENABLE          => VIRTUAL_DEBUG_ENABLE,
         CARD_ID_WIDTH       => FPGA_ID_WIDTH,
+        MISC_TOP2PCIE_WIDTH => MISC_TOP2PCIE_WIDTH,
+        MISC_PCIE2TOP_WIDTH => MISC_PCIE2TOP_WIDTH,
         DEVICE              => DEVICE
     )
     port map (
@@ -881,7 +913,10 @@ begin
         MI_DBG_WR          => mi_adc_wr  (MI_ADC_PORT_PCI_DBG),
         MI_DBG_DRD         => mi_adc_drd (MI_ADC_PORT_PCI_DBG),
         MI_DBG_ARDY        => mi_adc_ardy(MI_ADC_PORT_PCI_DBG),
-        MI_DBG_DRDY        => mi_adc_drdy(MI_ADC_PORT_PCI_DBG)
+        MI_DBG_DRDY        => mi_adc_drdy(MI_ADC_PORT_PCI_DBG),
+
+        MISC_TOP2PCIE      => MISC_TOP2PCIE,
+        MISC_PCIE2TOP      => MISC_PCIE2TOP
     );
 
     cdc_pcie_up_g: for i in 0 to PCIE_ENDPOINTS-1 generate
@@ -1293,6 +1328,8 @@ begin
         MI_ADDR_WIDTH         => MI_ADDR_WIDTH,
         FPGA_ID_WIDTH         => FPGA_ID_WIDTH,
         RESET_WIDTH           => RESET_WIDTH,
+        MISC_TOP2APP_WIDTH    => MISC_TOP2APP_WIDTH,
+        MISC_APP2TOP_WIDTH    => MISC_APP2TOP_WIDTH,
         BOARD                 => BOARD,
         DEVICE                => DEVICE
     )
@@ -1466,7 +1503,10 @@ begin
         MI_WR              => mi_adc_wr(MI_ADC_PORT_USERAPP),
         MI_DRD             => mi_adc_drd(MI_ADC_PORT_USERAPP),
         MI_ARDY            => mi_adc_ardy(MI_ADC_PORT_USERAPP),
-        MI_DRDY            => mi_adc_drdy(MI_ADC_PORT_USERAPP)
+        MI_DRDY            => mi_adc_drdy(MI_ADC_PORT_USERAPP),
+
+        MISC_TOP2APP           => MISC_TOP2APP,
+        MISC_APP2TOP           => MISC_APP2TOP
     );
 
     -- =========================================================================
@@ -1505,6 +1545,8 @@ begin
         LANE_RX_POLARITY  => ETH_LANE_RXPOLARITY,
         LANE_TX_POLARITY  => ETH_LANE_TXPOLARITY,
         RESET_WIDTH       => 1              ,
+        MISC_TOP2NET_WIDTH => MISC_TOP2NET_WIDTH,
+        MISC_NET2TOP_WIDTH => MISC_NET2TOP_WIDTH,
         DEVICE            => DEVICE         ,
         BOARD             => BOARD          ,
 
@@ -1606,7 +1648,10 @@ begin
         TSU_CLK         => tsu_clk,
         TSU_RST         => tsu_rst,
         TSU_TS_NS       => tsu_ns,
-        TSU_TS_DV       => tsu_dv
+        TSU_TS_DV       => tsu_dv,
+
+        MISC_TOP2NET    => MISC_TOP2NET,
+        MISC_NET2TOP    => MISC_NET2TOP
     );
 
     eth_led_ctrl_i: entity work.ETH_LED_CTRL_TOP