rx_dma_calypte_hdr_manager [FEATURE]: activate relaxed ordering for R…

…Q transactions
CESNET · Nov 6, 2024 · 6f255e2 · 6f255e2
1 parent 3e839f9
commit 6f255e2
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/comp/dma/dma_calypte/comp/rx/comp/hdr_manager/rx_dma_calypte_hdr_manager.vhd b/comp/dma/dma_calypte/comp/rx/comp/hdr_manager/rx_dma_calypte_hdr_manager.vhd
@@ -774,7 +774,7 @@ begin
             IN_VFID       => (others => '0'),
             IN_TAG        => (others => '0'),
             IN_DW_CNT     => std_logic_vector(to_unsigned(DATA_SEGMENT_SIZE/4, 11)),
-            IN_ATTRIBUTES => "000",
+            IN_ATTRIBUTES => "010",
             IN_FBE        => "1111",
             IN_LBE        => "1111",
             IN_ADDR_LEN   => pcie_addr_len_data_tran,
@@ -820,7 +820,7 @@ begin
             IN_VFID       => (others => '0'),
             IN_TAG        => (others => '0'),
             IN_DW_CNT     => std_logic_vector(to_unsigned(8/4, 11)),
-            IN_ATTRIBUTES => "000",
+            IN_ATTRIBUTES => "010",
             IN_FBE        => "1111",
             IN_LBE        => "1111",
             IN_ADDR_LEN   => pcie_addr_len_dma_hdr_tran,

diff --git a/comp/dma/dma_calypte/comp/rx/uvm/tbench/env/model.sv b/comp/dma/dma_calypte/comp/rx/uvm/tbench/env/model.sv
@@ -163,7 +163,7 @@ class model #(CHANNELS, PKT_SIZE_MAX, META_WIDTH, DEVICE) extends uvm_component;
     function void get_pcie_header(int unsigned packet_size, logic [64-1:0] addr, output logic[32-1 : 0] header[], output logic[168-1 : 0] meta);
         logic [2-1:0]  at       = 0;
         logic [1-1:0]  ecrc     = 0;
-        logic [3-1:0]  attr     = 0;
+        logic [3-1:0]  attr     = 2;
         logic [3-1:0]  tc       = 0;
         logic [1-1:0]  rq_id_enabled = 0;
         logic [16-1:0] cm_id    = 0; //compleater ID