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devel/_sources/index.rst.txt

@@ -25,9 +25,13 @@ The **Network Development Kit (NDK) for FPGAs** is a comprehensive framework des
 for the rapid and efficient development of FPGA-accelerated network applications. Optimized
 for scalability and high throughput, the NDK supports speeds up to **400 Gigabit Ethernet**.
 
+.. note::
+
+    New features and changes in the latest version of NDK-FPGA are described in the `CHANGELOG.md file <https://github.com/CESNET/ndk-fpga/blob/devel/CHANGELOG.md>`_.
+
 --------
 
-The NDK provides a minimal example application. The **NDK Minimal Application**
+The NDK-FPGA provides a minimal example application. The **NDK Minimal Application**
 demonstrates how to build an FPGA application using the NDK and serves as a starting point
 for your own development. The minimal application doesn't process network packets; it simply
 sends and receives them. If a DMA IP is enabled (see the :ref:`DMA Module <ndk_dma>`),
@@ -44,7 +48,7 @@ Other example applications will be added in the future, stay tuned!
 
 --------
 
-In addition, the NDK provides a collection of reusable components, some of which are vendor and
+In addition, the NDK-FPGA provides a collection of reusable components, some of which are vendor and
 vendor- and tool-independent, while others are optimized for specific FPGA vendors and architectures.
 For transferring packets (frames) and auxiliary data at such high rates, the NDK uses its own set of what are called
 "multibuses" that can transfer multiple frames and values, respectively, within a single clock cycle.
@@ -87,7 +91,7 @@ it also provides converters:
 
 --------
 
-The NDK supports a wide range of FPGA cards, providing access to features such as DDR and HBM
+The NDK-FPGA supports a wide range of FPGA cards, providing access to features such as DDR and HBM
 memories, PCIe, and Ethernet in your applications. However, different applications may only
 support a subset of these cards. A complete list of supported FPGA cards can be found below
 (minimal app supports all of them).
@@ -114,20 +118,19 @@ support a subset of these cards. A complete list of supported FPGA cards can be
 
 --------
 
-NDK provides two implementations of DMA IPs:
+NDK-FPGA supports two implementations of DMA IPs:
 
 * DMA Medusa
 * DMA Calypte
 
-DMA Medusa is a state-of-the-art DMA module that supports up to 400Gbps of throughput to
+DMA Medusa is a state-of-the-art DMA module that supports up to 400 Gbps of throughput to
 host memory. DMA Calypte is an open-source low-latency DMA supporting throughput up
-to tens of Gigabits per second. However, the DMA Calypte is still under development
-and is not yet officially released (stay tuned).
-
-.. warning::
+to 100 Gbps.
 
-    The DMA Medusa IP is not included in the open-source version of the NDK. `You can obtain the full NDK package, including DMA Medusa IP and professional support, from our partner BrnoLogic. <https://support.brnologic.com/>`_
+.. note::
 
+    The DMA Medusa IP is not part of the open-source NDK-FPGA.
+    For more information about IP availability, `see the section Partners in README.md file <https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners>`_.
 
 .. image:: img/liberouter_logo.svg
     :align: center

devel/_sources/ndk_core/doc/dma.rst.txt

@@ -11,7 +11,8 @@ The DMA module is a wrapper containing the DMA controller (DMA IP), auxiliary, a
 
 .. note::
 
-    The DMA Medusa IP is not part of the open-source NDK. `You can get the NDK, including the DMA Medusa IP and professional support, through our partner BrnoLogic. <https://support.brnologic.com/>`_
+    The DMA Medusa IP is not part of the open-source NDK-FPGA.
+    For more information about IP availability, `see the section Partners in README.md file <https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners>`_.
 
 Each DMA stream consists of two buses: the :ref:`MFB bus <mfb_bus>` is used to transfer data packets, the :ref:`MVB bus <mvb_bus>` is used to transfer DMA instructions to each packet. How a user application should properly use these buses is described in :ref:`The Application chapter <ndk_app>`.
 

devel/_sources/ndk_core/doc/performance.rst.txt

@@ -44,6 +44,11 @@ The throughput test is performed in three phases:
     :align: center
     :width: 100 %
 
+.. note::
+
+    The DMA Medusa IP is not part of the open-source NDK-FPGA.
+    For more information about IP availability, `see the section Partners in README.md file <https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners>`_.
+
 DMA Calypte IP
 **************
 

devel/index.html

@@ -126,8 +126,12 @@ <h1>Overview<a class="headerlink" href="#overview" title="Link to this heading">
 <p>The <strong>Network Development Kit (NDK) for FPGAs</strong> is a comprehensive framework designed
 for the rapid and efficient development of FPGA-accelerated network applications. Optimized
 for scalability and high throughput, the NDK supports speeds up to <strong>400 Gigabit Ethernet</strong>.</p>
+<div class="admonition note">
+<p class="admonition-title">Note</p>
+<p>New features and changes in the latest version of NDK-FPGA are described in the <a class="reference external" href="https://github.com/CESNET/ndk-fpga/blob/devel/CHANGELOG.md">CHANGELOG.md file</a>.</p>
+</div>
 <hr class="docutils" />
-<p>The NDK provides a minimal example application. The <strong>NDK Minimal Application</strong>
+<p>The NDK-FPGA provides a minimal example application. The <strong>NDK Minimal Application</strong>
 demonstrates how to build an FPGA application using the NDK and serves as a starting point
 for your own development. The minimal application doesn’t process network packets; it simply
 sends and receives them. If a DMA IP is enabled (see the <a class="reference internal" href="ndk_core/doc/dma.html#ndk-dma"><span class="std std-ref">DMA Module</span></a>),
@@ -141,7 +145,7 @@ <h1>Overview<a class="headerlink" href="#overview" title="Link to this heading">
 </ul>
 </div>
 <hr class="docutils" />
-<p>In addition, the NDK provides a collection of reusable components, some of which are vendor and
+<p>In addition, the NDK-FPGA provides a collection of reusable components, some of which are vendor and
 vendor- and tool-independent, while others are optimized for specific FPGA vendors and architectures.
 For transferring packets (frames) and auxiliary data at such high rates, the NDK uses its own set of what are called
 “multibuses” that can transfer multiple frames and values, respectively, within a single clock cycle.
@@ -181,7 +185,7 @@ <h1>Overview<a class="headerlink" href="#overview" title="Link to this heading">
 </ul>
 </div>
 <hr class="docutils" />
-<p>The NDK supports a wide range of FPGA cards, providing access to features such as DDR and HBM
+<p>The NDK-FPGA supports a wide range of FPGA cards, providing access to features such as DDR and HBM
 memories, PCIe, and Ethernet in your applications. However, different applications may only
 support a subset of these cards. A complete list of supported FPGA cards can be found below
 (minimal app supports all of them).</p>
@@ -205,18 +209,18 @@ <h1>Overview<a class="headerlink" href="#overview" title="Link to this heading">
 </ul>
 </div>
 <hr class="docutils" />
-<p>NDK provides two implementations of DMA IPs:</p>
+<p>NDK-FPGA supports two implementations of DMA IPs:</p>
 <ul class="simple">
 <li><p>DMA Medusa</p></li>
 <li><p>DMA Calypte</p></li>
 </ul>
-<p>DMA Medusa is a state-of-the-art DMA module that supports up to 400Gbps of throughput to
+<p>DMA Medusa is a state-of-the-art DMA module that supports up to 400 Gbps of throughput to
 host memory. DMA Calypte is an open-source low-latency DMA supporting throughput up
-to tens of Gigabits per second. However, the DMA Calypte is still under development
-and is not yet officially released (stay tuned).</p>
-<div class="admonition warning">
-<p class="admonition-title">Warning</p>
-<p>The DMA Medusa IP is not included in the open-source version of the NDK. <a class="reference external" href="https://support.brnologic.com/">You can obtain the full NDK package, including DMA Medusa IP and professional support, from our partner BrnoLogic.</a></p>
+to 100 Gbps.</p>
+<div class="admonition note">
+<p class="admonition-title">Note</p>
+<p>The DMA Medusa IP is not part of the open-source NDK-FPGA.
+For more information about IP availability, <a class="reference external" href="https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners">see the section Partners in README.md file</a>.</p>
 </div>
 <a class="reference internal image-reference" href="_images/liberouter_logo.svg"><img alt="_images/liberouter_logo.svg" class="align-center" src="_images/liberouter_logo.svg" style="width: 50%;" />
 </a>

devel/ndk_core/doc/dma.html

@@ -141,7 +141,8 @@
 </ul>
 <div class="admonition note">
 <p class="admonition-title">Note</p>
-<p>The DMA Medusa IP is not part of the open-source NDK. <a class="reference external" href="https://support.brnologic.com/">You can get the NDK, including the DMA Medusa IP and professional support, through our partner BrnoLogic.</a></p>
+<p>The DMA Medusa IP is not part of the open-source NDK-FPGA.
+For more information about IP availability, <a class="reference external" href="https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners">see the section Partners in README.md file</a>.</p>
 </div>
 <p>Each DMA stream consists of two buses: the <a class="reference internal" href="../../comp/mfb_tools/readme.html#mfb-bus"><span class="std std-ref">MFB bus</span></a> is used to transfer data packets, the <a class="reference internal" href="../../comp/mvb_tools/readme.html#mvb-bus"><span class="std std-ref">MVB bus</span></a> is used to transfer DMA instructions to each packet. How a user application should properly use these buses is described in <a class="reference internal" href="app.html#ndk-app"><span class="std std-ref">The Application chapter</span></a>.</p>
 <p>The DMA module optionally includes a <a class="reference internal" href="../../comp/mfb_tools/debug/gen_loop_switch/readme.html#gls-debug"><span class="std std-ref">Gen Loop Switch (GLS) module</span></a> for each DMA stream. The GLS module is used for debugging, contains packet generators and allows to enable loopback modes. The GLS module can be controlled through MI requests.</p>

devel/ndk_core/doc/performance.html

@@ -158,6 +158,11 @@ <h2>DMA Medusa IP<a class="headerlink" href="#dma-medusa-ip" title="Link to this
 </a>
 <a class="reference internal image-reference" href="../../_images/perf_report_dma_medusa_pps.svg"><img alt="../../_images/perf_report_dma_medusa_pps.svg" class="align-center" src="../../_images/perf_report_dma_medusa_pps.svg" style="width: 100%;" />
 </a>
+<div class="admonition note">
+<p class="admonition-title">Note</p>
+<p>The DMA Medusa IP is not part of the open-source NDK-FPGA.
+For more information about IP availability, <a class="reference external" href="https://github.com/CESNET/ndk-fpga/blob/devel/README.md#partners">see the section Partners in README.md file</a>.</p>
+</div>
 </section>
 <section id="dma-calypte-ip">
 <h2>DMA Calypte IP<a class="headerlink" href="#dma-calypte-ip" title="Link to this heading"></a></h2>