Merge branch 'cabal_ia440_ddr4' into 'devel'

DDR4 for IA-440i card

See merge request ndk/ndk-fpga!147

cards/bittware/ia-440i/config/card_conf.tcl

@@ -83,4 +83,6 @@ set TSU_ENABLE true
 # ------------------------------------------------------------------------------
 # DDR4 parameters:
 # ------------------------------------------------------------------------------
-set MEM_PORTS 0
+
+# The allowed values for the number of memory ports are 0 or 2.
+set MEM_PORTS 2

cards/bittware/ia-440i/config/card_const.tcl

@@ -42,6 +42,10 @@ Allowed PCIe configurations:
 - 1xGen5x8x8 -- PCIE_GEN=5, PCIE_ENDPOINTS=2, PCIE_ENDPOINT_MODE=1 (for DMA Medusa)"
 }
 
+if {!(($MEM_PORTS == 0) || ($MEM_PORTS == 2)) } {
+    error "Unsupported value MEM_PORTS=$MEM_PORTS. Allowed values are only: 0 or 2."
+}
+
 # ------------------------------------------------------------------------------
 # Other parameters:
 # ------------------------------------------------------------------------------

cards/bittware/ia-440i/constr/ddr4.qsf

@@ -0,0 +1,279 @@
+# ddr4.qsf
+# Copyright (C) 2023 CESNET z. s. p. o.
+# Author(s): Jakub Cabal <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+# DDR4 - P0
+# ==============================================================================
+
+set_location_assignment PIN_CL7  -to DDR4_P0_REF_CLK
+set_location_assignment PIN_CK8  -to "DDR4_P0_REF_CLK(n)"
+set_location_assignment PIN_CG13 -to DDR4_P0_CK[0]
+set_location_assignment PIN_CH14 -to DDR4_P0_CK_N[0]
+set_location_assignment PIN_CC17 -to DDR4_P0_A[0]
+set_location_assignment PIN_CB18 -to DDR4_P0_A[1]
+set_location_assignment PIN_CC15 -to DDR4_P0_A[2]
+set_location_assignment PIN_CB16 -to DDR4_P0_A[3]
+set_location_assignment PIN_CE15 -to DDR4_P0_A[4]
+set_location_assignment PIN_CF16 -to DDR4_P0_A[5]
+set_location_assignment PIN_CE17 -to DDR4_P0_A[6]
+set_location_assignment PIN_CF18 -to DDR4_P0_A[7]
+set_location_assignment PIN_CE13 -to DDR4_P0_A[8]
+set_location_assignment PIN_CF14 -to DDR4_P0_A[9]
+set_location_assignment PIN_CC13 -to DDR4_P0_A[10]
+set_location_assignment PIN_CB14 -to DDR4_P0_A[11]
+set_location_assignment PIN_CK12 -to DDR4_P0_A[12]
+set_location_assignment PIN_CL9  -to DDR4_P0_A[13]
+set_location_assignment PIN_CK10 -to DDR4_P0_A[14]
+set_location_assignment PIN_CG7  -to DDR4_P0_A[15]
+set_location_assignment PIN_CH8  -to DDR4_P0_A[16]
+set_location_assignment PIN_CH16 -to DDR4_P0_ACT_N[0]
+set_location_assignment PIN_CH10 -to DDR4_P0_BA[0]
+set_location_assignment PIN_CG11 -to DDR4_P0_BA[1]
+set_location_assignment PIN_CH12 -to DDR4_P0_BG[0]
+set_location_assignment PIN_CL17 -to DDR4_P0_BG[1]
+set_location_assignment PIN_CG17 -to DDR4_P0_CKE[0]
+set_location_assignment PIN_CG15 -to DDR4_P0_CS_N[0]
+set_location_assignment PIN_CL15 -to DDR4_P0_ODT[0]
+set_location_assignment PIN_CK18 -to DDR4_P0_RESET_N[0]
+set_location_assignment PIN_CK14 -to DDR4_P0_PAR[0]
+set_location_assignment PIN_CG9  -to DDR4_P0_ALERT_N[0]
+set_location_assignment PIN_CR3  -to DDR4_P0_DQS_P[0]
+set_location_assignment PIN_CT4  -to DDR4_P0_DQS_N[0]
+set_location_assignment PIN_CR9  -to DDR4_P0_DQS_P[1]
+set_location_assignment PIN_CT10 -to DDR4_P0_DQS_N[1]
+set_location_assignment PIN_DA9  -to DDR4_P0_DQS_P[2]
+set_location_assignment PIN_CY10 -to DDR4_P0_DQS_N[2]
+set_location_assignment PIN_CR15 -to DDR4_P0_DQS_P[3]
+set_location_assignment PIN_CT16 -to DDR4_P0_DQS_N[3]
+set_location_assignment PIN_CE9  -to DDR4_P0_DQS_P[4]
+set_location_assignment PIN_CF10 -to DDR4_P0_DQS_N[4]
+set_location_assignment PIN_BR3  -to DDR4_P0_DQS_P[5]
+set_location_assignment PIN_BT4  -to DDR4_P0_DQS_N[5]
+set_location_assignment PIN_CA3  -to DDR4_P0_DQS_P[6]
+set_location_assignment PIN_BY4  -to DDR4_P0_DQS_N[6]
+set_location_assignment PIN_CE3  -to DDR4_P0_DQS_P[7]
+set_location_assignment PIN_CF4  -to DDR4_P0_DQS_N[7]
+set_location_assignment PIN_CL3  -to DDR4_P0_DQS_P[8]
+set_location_assignment PIN_CK4  -to DDR4_P0_DQS_N[8]
+set_location_assignment PIN_CN1  -to DDR4_P0_DBI_N[0]
+set_location_assignment PIN_CN9  -to DDR4_P0_DBI_N[1]
+set_location_assignment PIN_CU9  -to DDR4_P0_DBI_N[2]
+set_location_assignment PIN_CN15 -to DDR4_P0_DBI_N[3]
+set_location_assignment PIN_CC7  -to DDR4_P0_DBI_N[4]
+set_location_assignment PIN_BN1  -to DDR4_P0_DBI_N[5]
+set_location_assignment PIN_BU1  -to DDR4_P0_DBI_N[6]
+set_location_assignment PIN_CC1  -to DDR4_P0_DBI_N[7]
+set_location_assignment PIN_CG1  -to DDR4_P0_DBI_N[8]
+set_location_assignment PIN_CM6  -to DDR4_P0_DQ[0]
+set_location_assignment PIN_CT2  -to DDR4_P0_DQ[1]
+set_location_assignment PIN_CN5  -to DDR4_P0_DQ[2]
+set_location_assignment PIN_CR1  -to DDR4_P0_DQ[3]
+set_location_assignment PIN_CR5  -to DDR4_P0_DQ[4]
+set_location_assignment PIN_CN3  -to DDR4_P0_DQ[5]
+set_location_assignment PIN_CT6  -to DDR4_P0_DQ[6]
+set_location_assignment PIN_CM4  -to DDR4_P0_DQ[7]
+set_location_assignment PIN_CR11 -to DDR4_P0_DQ[8]
+set_location_assignment PIN_CN7  -to DDR4_P0_DQ[9]
+set_location_assignment PIN_CN11 -to DDR4_P0_DQ[10]
+set_location_assignment PIN_CM8  -to DDR4_P0_DQ[11]
+set_location_assignment PIN_CM12 -to DDR4_P0_DQ[12]
+set_location_assignment PIN_CR7  -to DDR4_P0_DQ[13]
+set_location_assignment PIN_CT12 -to DDR4_P0_DQ[14]
+set_location_assignment PIN_CT8  -to DDR4_P0_DQ[15]
+set_location_assignment PIN_CY8  -to DDR4_P0_DQ[16]
+set_location_assignment PIN_DA11 -to DDR4_P0_DQ[17]
+set_location_assignment PIN_CU11 -to DDR4_P0_DQ[18]
+set_location_assignment PIN_DA7  -to DDR4_P0_DQ[19]
+set_location_assignment PIN_CV8  -to DDR4_P0_DQ[20]
+set_location_assignment PIN_CV12 -to DDR4_P0_DQ[21]
+set_location_assignment PIN_CU7  -to DDR4_P0_DQ[22]
+set_location_assignment PIN_CY12 -to DDR4_P0_DQ[23]
+set_location_assignment PIN_CM14 -to DDR4_P0_DQ[24]
+set_location_assignment PIN_CT18 -to DDR4_P0_DQ[25]
+set_location_assignment PIN_CT14 -to DDR4_P0_DQ[26]
+set_location_assignment PIN_CN13 -to DDR4_P0_DQ[27]
+set_location_assignment PIN_CN17 -to DDR4_P0_DQ[28]
+set_location_assignment PIN_CR17 -to DDR4_P0_DQ[29]
+set_location_assignment PIN_CM18 -to DDR4_P0_DQ[30]
+set_location_assignment PIN_CR13 -to DDR4_P0_DQ[31]
+set_location_assignment PIN_CB12 -to DDR4_P0_DQ[32]
+set_location_assignment PIN_CF8  -to DDR4_P0_DQ[33]
+set_location_assignment PIN_CC11 -to DDR4_P0_DQ[34]
+set_location_assignment PIN_CC9  -to DDR4_P0_DQ[35]
+set_location_assignment PIN_CE11 -to DDR4_P0_DQ[36]
+set_location_assignment PIN_CE7  -to DDR4_P0_DQ[37]
+set_location_assignment PIN_CF12 -to DDR4_P0_DQ[38]
+set_location_assignment PIN_CB10 -to DDR4_P0_DQ[39]
+set_location_assignment PIN_BT6  -to DDR4_P0_DQ[40]
+set_location_assignment PIN_BM4  -to DDR4_P0_DQ[41]
+set_location_assignment PIN_BR5  -to DDR4_P0_DQ[42]
+set_location_assignment PIN_BN3  -to DDR4_P0_DQ[43]
+set_location_assignment PIN_BM6  -to DDR4_P0_DQ[44]
+set_location_assignment PIN_BR1  -to DDR4_P0_DQ[45]
+set_location_assignment PIN_BN5  -to DDR4_P0_DQ[46]
+set_location_assignment PIN_BT2  -to DDR4_P0_DQ[47]
+set_location_assignment PIN_BV6  -to DDR4_P0_DQ[48]
+set_location_assignment PIN_BY2  -to DDR4_P0_DQ[49]
+set_location_assignment PIN_BU5  -to DDR4_P0_DQ[50]
+set_location_assignment PIN_BU3  -to DDR4_P0_DQ[51]
+set_location_assignment PIN_CA5  -to DDR4_P0_DQ[52]
+set_location_assignment PIN_CA1  -to DDR4_P0_DQ[53]
+set_location_assignment PIN_BY6  -to DDR4_P0_DQ[54]
+set_location_assignment PIN_BV4  -to DDR4_P0_DQ[55]
+set_location_assignment PIN_CB6  -to DDR4_P0_DQ[56]
+set_location_assignment PIN_CF2  -to DDR4_P0_DQ[57]
+set_location_assignment PIN_CC5  -to DDR4_P0_DQ[58]
+set_location_assignment PIN_CE1  -to DDR4_P0_DQ[59]
+set_location_assignment PIN_CB4  -to DDR4_P0_DQ[60]
+set_location_assignment PIN_CF6  -to DDR4_P0_DQ[61]
+set_location_assignment PIN_CC3  -to DDR4_P0_DQ[62]
+set_location_assignment PIN_CE5  -to DDR4_P0_DQ[63]
+set_location_assignment PIN_CK6  -to DDR4_P0_DQ[64]
+set_location_assignment PIN_CK2  -to DDR4_P0_DQ[65]
+set_location_assignment PIN_CH4  -to DDR4_P0_DQ[66]
+set_location_assignment PIN_CL5  -to DDR4_P0_DQ[67]
+set_location_assignment PIN_CG5  -to DDR4_P0_DQ[68]
+set_location_assignment PIN_CL1  -to DDR4_P0_DQ[69]
+set_location_assignment PIN_CH6  -to DDR4_P0_DQ[70]
+set_location_assignment PIN_CG3  -to DDR4_P0_DQ[71]
+set_location_assignment PIN_CL11 -to DDR4_P0_OCT_RZQIN
+
+# ==============================================================================
+# DDR4 - P0
+# ==============================================================================
+
+set_location_assignment PIN_L7   -to DDR4_P1_REF_CLK
+set_location_assignment PIN_M8   -to "DDR4_P1_REF_CLK(n)"
+set_location_assignment PIN_L13  -to DDR4_P1_CK[0]
+set_location_assignment PIN_M14  -to DDR4_P1_CK_N[0]
+set_location_assignment PIN_J11  -to DDR4_P1_A[0]
+set_location_assignment PIN_K12  -to DDR4_P1_A[1]
+set_location_assignment PIN_G11  -to DDR4_P1_A[2]
+set_location_assignment PIN_F12  -to DDR4_P1_A[3]
+set_location_assignment PIN_G9   -to DDR4_P1_A[4]
+set_location_assignment PIN_F10  -to DDR4_P1_A[5]
+set_location_assignment PIN_J9   -to DDR4_P1_A[6]
+set_location_assignment PIN_K10  -to DDR4_P1_A[7]
+set_location_assignment PIN_G7   -to DDR4_P1_A[8]
+set_location_assignment PIN_F8   -to DDR4_P1_A[9]
+set_location_assignment PIN_J7   -to DDR4_P1_A[10]
+set_location_assignment PIN_K8   -to DDR4_P1_A[11]
+set_location_assignment PIN_M12  -to DDR4_P1_A[12]
+set_location_assignment PIN_L9   -to DDR4_P1_A[13]
+set_location_assignment PIN_M10  -to DDR4_P1_A[14]
+set_location_assignment PIN_R9   -to DDR4_P1_A[15]
+set_location_assignment PIN_P10  -to DDR4_P1_A[16]
+set_location_assignment PIN_P18  -to DDR4_P1_ACT_N[0]
+set_location_assignment PIN_P12  -to DDR4_P1_BA[0]
+set_location_assignment PIN_R7   -to DDR4_P1_BA[1]
+set_location_assignment PIN_P8   -to DDR4_P1_BG[0]
+set_location_assignment PIN_L17  -to DDR4_P1_BG[1]
+set_location_assignment PIN_R15  -to DDR4_P1_CKE[0]
+set_location_assignment PIN_R17  -to DDR4_P1_CS_N[0]
+set_location_assignment PIN_L15  -to DDR4_P1_ODT[0]
+set_location_assignment PIN_M18  -to DDR4_P1_RESET_N[0]
+set_location_assignment PIN_P14  -to DDR4_P1_PAR[0]
+set_location_assignment PIN_R11  -to DDR4_P1_ALERT_N[0]
+set_location_assignment PIN_G15  -to DDR4_P1_DQS_P[0]
+set_location_assignment PIN_F16  -to DDR4_P1_DQS_N[0]
+set_location_assignment PIN_G21  -to DDR4_P1_DQS_P[1]
+set_location_assignment PIN_F22  -to DDR4_P1_DQS_N[1]
+set_location_assignment PIN_L21  -to DDR4_P1_DQS_P[2]
+set_location_assignment PIN_M22  -to DDR4_P1_DQS_N[2]
+set_location_assignment PIN_L27  -to DDR4_P1_DQS_P[3]
+set_location_assignment PIN_M28  -to DDR4_P1_DQS_N[3]
+set_location_assignment PIN_A9   -to DDR4_P1_DQS_P[4]
+set_location_assignment PIN_B10  -to DDR4_P1_DQS_N[4]
+set_location_assignment PIN_L3   -to DDR4_P1_DQS_P[5]
+set_location_assignment PIN_M4   -to DDR4_P1_DQS_N[5]
+set_location_assignment PIN_G3   -to DDR4_P1_DQS_P[6]
+set_location_assignment PIN_F4   -to DDR4_P1_DQS_N[6]
+set_location_assignment PIN_U3   -to DDR4_P1_DQS_P[7]
+set_location_assignment PIN_T4   -to DDR4_P1_DQS_N[7]
+set_location_assignment PIN_U9   -to DDR4_P1_DQS_P[8]
+set_location_assignment PIN_T10  -to DDR4_P1_DQS_N[8]
+set_location_assignment PIN_J15  -to DDR4_P1_DM[0]
+set_location_assignment PIN_J21  -to DDR4_P1_DM[1]
+set_location_assignment PIN_R21  -to DDR4_P1_DM[2]
+set_location_assignment PIN_R27  -to DDR4_P1_DM[3]
+set_location_assignment PIN_E9   -to DDR4_P1_DM[4]
+set_location_assignment PIN_R1   -to DDR4_P1_DM[5]
+set_location_assignment PIN_J1   -to DDR4_P1_DM[6]
+set_location_assignment PIN_W1   -to DDR4_P1_DM[7]
+set_location_assignment PIN_W7   -to DDR4_P1_DM[8]
+set_location_assignment PIN_G17  -to DDR4_P1_DQ[0]
+set_location_assignment PIN_F14  -to DDR4_P1_DQ[1]
+set_location_assignment PIN_J17  -to DDR4_P1_DQ[2]
+set_location_assignment PIN_G13  -to DDR4_P1_DQ[3]
+set_location_assignment PIN_F18  -to DDR4_P1_DQ[4]
+set_location_assignment PIN_J13  -to DDR4_P1_DQ[5]
+set_location_assignment PIN_K18  -to DDR4_P1_DQ[6]
+set_location_assignment PIN_K14  -to DDR4_P1_DQ[7]
+set_location_assignment PIN_G19  -to DDR4_P1_DQ[8]
+set_location_assignment PIN_K24  -to DDR4_P1_DQ[9]
+set_location_assignment PIN_J19  -to DDR4_P1_DQ[10]
+set_location_assignment PIN_G23  -to DDR4_P1_DQ[11]
+set_location_assignment PIN_K20  -to DDR4_P1_DQ[12]
+set_location_assignment PIN_F24  -to DDR4_P1_DQ[13]
+set_location_assignment PIN_F20  -to DDR4_P1_DQ[14]
+set_location_assignment PIN_J23  -to DDR4_P1_DQ[15]
+set_location_assignment PIN_P24  -to DDR4_P1_DQ[16]
+set_location_assignment PIN_P20  -to DDR4_P1_DQ[17]
+set_location_assignment PIN_M24  -to DDR4_P1_DQ[18]
+set_location_assignment PIN_M20  -to DDR4_P1_DQ[19]
+set_location_assignment PIN_L19  -to DDR4_P1_DQ[20]
+set_location_assignment PIN_R19  -to DDR4_P1_DQ[21]
+set_location_assignment PIN_L23  -to DDR4_P1_DQ[22]
+set_location_assignment PIN_R23  -to DDR4_P1_DQ[23]
+set_location_assignment PIN_L29  -to DDR4_P1_DQ[24]
+set_location_assignment PIN_M26  -to DDR4_P1_DQ[25]
+set_location_assignment PIN_R29  -to DDR4_P1_DQ[26]
+set_location_assignment PIN_R25  -to DDR4_P1_DQ[27]
+set_location_assignment PIN_P30  -to DDR4_P1_DQ[28]
+set_location_assignment PIN_L25  -to DDR4_P1_DQ[29]
+set_location_assignment PIN_M30  -to DDR4_P1_DQ[30]
+set_location_assignment PIN_P26  -to DDR4_P1_DQ[31]
+set_location_assignment PIN_B8   -to DDR4_P1_DQ[32]
+set_location_assignment PIN_B12  -to DDR4_P1_DQ[33]
+set_location_assignment PIN_A11  -to DDR4_P1_DQ[34]
+set_location_assignment PIN_D12  -to DDR4_P1_DQ[35]
+set_location_assignment PIN_E7   -to DDR4_P1_DQ[36]
+set_location_assignment PIN_E11  -to DDR4_P1_DQ[37]
+set_location_assignment PIN_A7   -to DDR4_P1_DQ[38]
+set_location_assignment PIN_D8   -to DDR4_P1_DQ[39]
+set_location_assignment PIN_P6   -to DDR4_P1_DQ[40]
+set_location_assignment PIN_P4   -to DDR4_P1_DQ[41]
+set_location_assignment PIN_L5   -to DDR4_P1_DQ[42]
+set_location_assignment PIN_R3   -to DDR4_P1_DQ[43]
+set_location_assignment PIN_M6   -to DDR4_P1_DQ[44]
+set_location_assignment PIN_M2   -to DDR4_P1_DQ[45]
+set_location_assignment PIN_R5   -to DDR4_P1_DQ[46]
+set_location_assignment PIN_L1   -to DDR4_P1_DQ[47]
+set_location_assignment PIN_G1   -to DDR4_P1_DQ[48]
+set_location_assignment PIN_K4   -to DDR4_P1_DQ[49]
+set_location_assignment PIN_G5   -to DDR4_P1_DQ[50]
+set_location_assignment PIN_J5   -to DDR4_P1_DQ[51]
+set_location_assignment PIN_F2   -to DDR4_P1_DQ[52]
+set_location_assignment PIN_F6   -to DDR4_P1_DQ[53]
+set_location_assignment PIN_J3   -to DDR4_P1_DQ[54]
+set_location_assignment PIN_K6   -to DDR4_P1_DQ[55]
+set_location_assignment PIN_T6   -to DDR4_P1_DQ[56]
+set_location_assignment PIN_W3   -to DDR4_P1_DQ[57]
+set_location_assignment PIN_W5   -to DDR4_P1_DQ[58]
+set_location_assignment PIN_Y4   -to DDR4_P1_DQ[59]
+set_location_assignment PIN_Y6   -to DDR4_P1_DQ[60]
+set_location_assignment PIN_T2   -to DDR4_P1_DQ[61]
+set_location_assignment PIN_U5   -to DDR4_P1_DQ[62]
+set_location_assignment PIN_U1   -to DDR4_P1_DQ[63]
+set_location_assignment PIN_U11  -to DDR4_P1_DQ[64]
+set_location_assignment PIN_Y10  -to DDR4_P1_DQ[65]
+set_location_assignment PIN_Y12  -to DDR4_P1_DQ[66]
+set_location_assignment PIN_W9   -to DDR4_P1_DQ[67]
+set_location_assignment PIN_T12  -to DDR4_P1_DQ[68]
+set_location_assignment PIN_T8   -to DDR4_P1_DQ[69]
+set_location_assignment PIN_W11  -to DDR4_P1_DQ[70]
+set_location_assignment PIN_U7   -to DDR4_P1_DQ[71]
+set_location_assignment PIN_L11  -to DDR4_P1_OCT_RZQIN

cards/bittware/ia-440i/src/Modules.tcl

@@ -38,6 +38,9 @@ set FTILE_ETH_IP_NAME "ftile_eth_[dict get $ETH_CONF $ARCHGRP_ARR(ETH_PORT_SPEED
 lappend IP_COMPONENTS [list  "clk"     "iopll"             "iopll_ip"             0      1]
 lappend IP_COMPONENTS [list  "misc"    "mailbox_client"    "mailbox_client_ip"    0      0]
 lappend IP_COMPONENTS [list  "misc"    "reset_release"     "reset_release_ip"     0      0]
+lappend IP_COMPONENTS [list  "mem"     "ddr4_calibration"  "ddr4_calibration"     0      0]
+lappend IP_COMPONENTS [list  "mem"     "onboard_ddr4"      "onboard_ddr4_0"       0      1]
+lappend IP_COMPONENTS [list  "mem"     "onboard_ddr4"      "onboard_ddr4_1"       1      1]
 lappend IP_COMPONENTS [list  "pcie"    "rtile_pcie"        $RTILE_PCIE_IP_NAME    0      1]
 
 if {$ARCHGRP_ARR(VIRTUAL_DEBUG_ENABLE)} {

cards/bittware/ia-440i/src/Quartus.inc.tcl

@@ -52,5 +52,5 @@ lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/general.qsf"
 lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/bmc.qsf"
 lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/pcie.qsf"
 lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/qsfp.qsf"
-#lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/ddr4.qsf"
+lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/ddr4.qsf"
 lappend SYNTH_FLAGS(CONSTR) "$CARD_BASE/constr/timing.sdc"