Merge branch 'gurka-feat-mvb_gate' into 'devel'

feat(mvb_tools): Add MVB gate component

See merge request ndk/ndk-fpga!105

comp/mvb_tools/flow/gate/Modules.tcl

@@ -0,0 +1,11 @@
+# Modules.tcl: Components include script
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Oliver Gurka <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+set MVB_FIFOX_BASE      "$OFM_PATH/comp/mvb_tools/storage/fifox"
+
+lappend COMPONENTS [list "MVB_FIFOX"      $MVB_FIFOX_BASE   "FULL"]
+
+set MOD "$MOD $ENTITY_BASE/mvb_gate.vhd"

comp/mvb_tools/flow/gate/mvb_gate.vhd

@@ -0,0 +1,86 @@
+-- mvb_gate.vhd: Gating for MVB
+-- Copyright (C) 2024 CESNET z. s. p. o.
+-- Author(s): Oliver Gurka <[email protected]>
+--
+-- SPDX-License-Identifier: BSD-3-Clause
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Simple gate for MVB bus. Has option for instation of FIFO,
+-- which can smooth out stopping of the bus.
+entity MVB_GATE is
+    generic(
+        ITEMS           :       natural := 4;
+        ITEM_WIDTH      :       natural := 8;
+        RX_FIFO_EN      :       boolean := false;
+        RX_FIFO_DEPTH   :       natural := 32;
+        DEVICE          :       string  := "AGILEX"
+    );
+    port(
+        CLK             : in    std_logic;
+        RESET           : in    std_logic;
+
+        -- ===============================================
+        -- RX MVB interface
+        -- ===============================================
+        RX_DATA         : in    std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0);
+        RX_VLD          : in    std_logic_vector(ITEMS-1 downto 0);
+        RX_SRC_RDY      : in    std_logic;
+        RX_DST_RDY      : out   std_logic;
+        -- ===============================================
+
+        -- ===============================================
+        -- TX MVB interface
+        -- ===============================================
+        TX_DATA         : out   std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0);
+        TX_VLD          : out   std_logic_vector(ITEMS-1 downto 0);
+        TX_SRC_RDY      : out   std_logic;
+        TX_DST_RDY      : in    std_logic;
+        -- ===============================================
+
+        -- When this signal is asserted, transmission from RX -> TX
+        -- is disabled.
+        STOP_EN         : in    std_logic
+    );
+end entity;
+
+architecture FULL of MVB_GATE is
+
+    signal rx_fifox_tx_data     : std_logic_vector(ITEMS*ITEM_WIDTH-1 downto 0);
+    signal rx_fifox_tx_vld      : std_logic_vector(ITEMS-1 downto 0);
+    signal rx_fifox_tx_src_rdy  : std_logic;
+    signal rx_fifox_tx_dst_rdy  : std_logic;
+
+begin
+
+    rx_fifo_i : entity work.MVB_FIFOX
+    generic map (
+        ITEMS       => ITEMS,
+        ITEM_WIDTH  => ITEM_WIDTH,
+        FIFO_DEPTH  => RX_FIFO_DEPTH,
+        RAM_TYPE    => "AUTO",
+        DEVICE      => DEVICE,
+        FAKE_FIFO   => not RX_FIFO_EN
+    ) port map (
+        CLK         => CLK,
+        RESET       => RESET,
+
+        RX_DATA     => RX_DATA,
+        RX_VLD      => RX_VLD,
+        RX_SRC_RDY  => RX_SRC_RDY,
+        RX_DST_RDY  => RX_DST_RDY,
+
+        TX_DATA     => rx_fifox_tx_data,
+        TX_VLD      => rx_fifox_tx_vld,
+        TX_SRC_RDY  => rx_fifox_tx_src_rdy,
+        TX_DST_RDY  => rx_fifox_tx_dst_rdy
+    );
+
+    TX_DATA              <= rx_fifox_tx_data;
+    TX_VLD               <= rx_fifox_tx_vld;
+    TX_SRC_RDY           <= rx_fifox_tx_src_rdy and not STOP_EN;
+    rx_fifox_tx_dst_rdy  <= TX_DST_RDY and not STOP_EN;
+
+end architecture;

comp/mvb_tools/flow/gate/readme.rst

@@ -0,0 +1,6 @@
+.. _mvb_gate:
+
+MVB Gate
+--------
+
+.. vhdl:autoentity:: MVB_GATE

comp/mvb_tools/flow/gate/synth/Makefile

@@ -0,0 +1,15 @@
+# Makefile: Makefile script to compile specified module
+# Copyright (C) 2024 CESNET z. s. p. o.
+# Author(s): Oliver Gurka <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+TOP_LEVEL_ENT=MVB_GATE
+SYNTH=quartus
+DEVICE=AGILEX
+
+all: comp
+
+include ../../../../../build/Makefile
+
+.PHONY: all

doc/source/mvb.rst

@@ -21,5 +21,6 @@ Components using the MFB bus are typically located in the ``comp/mvb_tools/`` di
    comp/mvb_tools/flow/operation/readme
    comp/mvb_tools/flow/merge_streams_ordered/readme
    comp/mvb_tools/flow/mvb2mfb/readme
+   comp/mvb_tools/flow/gate/readme
    comp/mvb_tools/storage/lookup_table/readme
    comp/mvb_tools/storage/fifox/readme