Fix crashes when multiple cpus are enabled - #1
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A210 is T-Head C9xx-derived, but never registered the TLB-flush illegal-instruction trap fixup that thead-generic.c install via thead_register_tlb_flush_trap_handler(). Without it, an SBI_EXT_RFENCE remote-fence call could make a hart execute a TLB-invalidation instruction sequence that traps as illegal instruction on this core. Select THEAD_C9XX_ERRATA for PLATFORM_ZHIHE_A210 to pull in the fixup trap handler and call it on every hart branch, matching thead_generic_cold_boot_allowed()'s pattern. Signed-off-by: Vitor Sato Eschholz <vsatoes@baylibre.com>
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August 26, 2026 14:25
SBI_PLATFORM_DEFAULT_HART_STACK_SIZE (8192) minus SBI_SCRATCH_SIZE (4096) left only ~4KB of usable M-mode stack per hart. On A210, when enabling multiple harts, a nested trap could overflow the 4KB budget into the adjacent hart's scratch/stack region. Bumping the default to 32768 gives ~28KB of usable per-hart stack, which was confirmed on A210 hardware to be more stable. Signed-off-by: Vitor Sato Eschholz <vsatoes@baylibre.com>
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