[feature]: support new instructions provided by armclang#2
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Add 3 prebuilt STM32CubeF1 STM32F103RB-Nucleo firmware compiled under Keil MDK + Arm Compiler 6 (armclang) as committed ELF (.axf) E2E fixtures, exercising armcc codegen alongside the existing gcc sample: - nucleo_f103rb_tim_timebase.ac6.axf (TIM UIF / interrupt) - nucleo_f103rb_uart_printf.ac6.axf (USART TX, printf retarget) - nucleo_f103rb_gpio_iotoggle.ac6.axf (GPIO toggle) Each boots clean (0 fault) at 2,000,000 steps; wired into ctest via test_firmware_armcc. CI has no Keil so binaries are committed; test/firmware/armcc/REGENERATE.md documents the AC5->AC6 migration recipe (uAC6=1, drop --C99, drop v6Lang) and the WSL-fs -> local-NTFS build constraint.
…ilies (T0)
cortex_m3_thumb32.cpp exceeded the DIRECTIVES 700-line cap (809 lines) and
the instruction-coverage work would push it further. Extract the eight
largest execute_32bit blocks into two family files:
cortex_m3_thumb32_dataproc.cpp — addsub-plain-imm, dataproc-imm,
dataproc-reg (shifted), shift-reg
cortex_m3_thumb32_loadstore.cpp — load/store-single, tbb/tbh,
strd/ldrd, stm/ldm
execute_32bit is now a thin dispatcher (masks unchanged, same order); the
rr/wr/br/bw operand lambdas are promoted to private members so the split-out
handlers reuse them. Pure move — 247/247 tests green, behavior unchanged.
thumb32.cpp 809->376; both new files <270.
Companion note for the T5c corpus (ce2f6ab): the AC5->AC6 migration recipe, the WSL-fs build wall, and the headless build flow.
LSLS/LSRS/ASRS/RORS (16-bit immediate, 16-bit register, and 32-bit register forms) called update_nz() which only touches N/Z, leaving C stale. ARMv7-M requires C = shifter carry-out (with the encoded-0=32, RRX, and shift-by->=32 special cases). Add a centralized thumb::barrel_shift(type, value, amount, carry_in) helper that returns both the shifted value and the carry-out, and route the three shift sites through it. Side fixes uncovered by centralizing: ASR-by-register >=32 used signed >>amount (UB) instead of sign-extension; ROR Rs==0 is now RRX (was a silent no-op). 5 new carry unit tests (read flags via MRS Rd,APSR). 252/252 green.
Extend Cortex-M3 Thumb-2 coverage: fix silent correctness bugs and implement base instructions that previously faulted. Silent errors fixed (computed/wrote wrong results without faulting): - register-offset load/store [Rn,Rm] computed r1+2 not r1+r2 - ORN.W reg dropped Rn; RSB.W flag operands reversed - LSR/ASR shift-by-32 left rm_val; CPSID/IE f hit PRIMASK - BKPT was a NOP; MUL.W Ra=15 folded raw PC; ADR.W used raw PC - TBH dispatch mask retained the H-bit; LDREX/STREX swallowed by STRD/LDRD Base instructions added (M3 scope): - ORN.W/MVN.W immediate; ROR/RRX shifted-register operand - SMLAL/UMLAL; LDRSB.W/LDRSH.W (sign-extend); CLZ/RBIT/REV.W family - SSAT/USAT (+ new APSR.Q bit 27); CLREX/NOP.W hints - MCR/MRC clean-fault (no coprocessor on M3) Nineteen targeted unit tests; ctest 271 green; all firmware E2E green.
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