VLSI internship at SMEClabs

Welcome to my VLSI internship repository at SMEC Labs. This repository contains a series of VHDL-based digital design modules that I developed and simulated as part of my internship training. These designs cover a wide range of fundamental building blocks used in modern digital systems.

📁 Project Overview

During this internship, I focused on the RTL (Register Transfer Level) design and simulation of essential digital logic components using VHDL. The projects demonstrate skills in structural and behavioral modeling, as well as a good understanding of testbenches for functional verification.

🛠️ Implemented Modules

The following VHDL modules were developed:

• Adders
  • Half Adder
  • Full Adder
• Arithmetic Logic Unit (ALU)
• Multiplexers
  • MUX (Multiplexer)
• Logic Gates
  • NOT Gate
  • NAND (implemented using AND gates)
  • AND Gate
  • OR Gate
• Flip-Flops
  • D Flip-Flop
  • JK Flip-Flop
  • SR Flip-Flop
  • T Flip-Flop
• Counters
  • 2-bit Counter using D Flip-Flop
  • Johnson Counter
  • Ring Counter
• Shift Registers
  • Bidirectional Shift Register
  • SISO (Serial-In Serial-Out)
  • PIPO (Parallel-In Parallel-Out)
• Encoders
  • Encoder

🧪 Testing

Each module includes a VHDL testbench to verify its correctness under various input conditions. Simulations were performed to confirm functional accuracy.

🚀 Tools & Technologies

• VHDL (primary design language)
• Simulation tools (ModelSim Mentor Graphics)
• Basic waveform analysis for debugging and validation

🎯 Learning Outcomes

• RTL design practices
• Modular VHDL coding
• Functional simulation and verification
• Digital system design thinking

📝 Assessment Tasks

As part of the internship evaluation, I implemented and verified the following modules:

1️⃣ Counter (Sequence 0010 to 1010)

• Description: A custom sequence counter counting from 0010 (2) to 1010 (10) in binary.
• Design Language: VHDL
• Waveform Screenshot:
  

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2️⃣ Shift Registers

a) Bidirectional Shift Register

• Description: A shift register capable of shifting data both left and right.
• Design Language: VHDL
• Waveform Screenshot:
  

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3️⃣ Counters

a) Johnson Counter

• Description: A Johnson counter generating a unique bit pattern through feedback.
• Design Language: VHDL
• Waveform Screenshot:
  

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4️⃣ Encoders

a) Encoder

• Description: Priority encoder to encode multiple inputs to binary output.
• Design Language: VHDL
• Waveform Screenshot:
  

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5️⃣ Flip-Flops

a) JK Flip-Flop

• Description: Standard JK flip-flop with asynchronous reset.
• Design Language: VHDL
• Waveform Screenshot:
  

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6️⃣ Arithmetic Logic Unit (ALU)

• Description: 4-bit ALU supporting basic arithmetic and logic operations.
• Design Language: VHDL
• Waveform Screenshot:
  

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7️⃣ Multiplexers

a) 4:1 MUX

• Description: 4-to-1 multiplexer with select lines and data inputs.
• Design Language: VHDL
• Waveform Screenshot:
  

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8️⃣ Adders

a) Full Adder

• Description: 1-bit full adder with sum and carry outputs.
• Design Language: VHDL
• Waveform Screenshot:
  

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9️⃣ Logic Gates

a) NAND Gate Using AND Gates

• Description: NAND function implemented structurally using AND and NOT gates.
• Design Language: VHDL
• Waveform Screenshot:
  

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