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# Question 26


Which ones of these instructions are incorrect and why?
```asm
mov [rax], 0
cmp [rdx], bl
mov bh, bl
mov al, al
add bpl, 9
add [9], spl
mov r8d, r9d
mov r3b, al
mov r9w, r2d
mov rcx, [rax + rbx + rdx]
mov r9, [r9 + 8*rax]
mov [r8+r7+10], 6
mov [r8+r7+10], r6
```


# Answer



The incorrect instructions are listed below:

```asm
mov [rax], 0 ; We don't know whether we should write 8, 4, 2 or 1 byte
; Change to e.g. `mov dword [rax], 0`
mov r3b, al ; NASM does not support r0-r7 names, only r8-r15
mov r9w, r2d ; NASM does not support r0-r7 names, only r8-r15
mov rcx, [rax + rbx + rdx] ; displacement should be an immediate value
; can not use register for it
mov [r8+r7+10], 6 ; No size specified, NASM does not support r7
mov [r8+r7+10], r6 ; NASM does not support r6 or r7
```



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# Question 32


Describe the effects of the following instructions:
\beginitemize
\item `sar `
\item `shr`
\item `xor`
\item `jmp`
\item `ja`, `jb` and similar ones.
\item `cmp`
\item `mov`
\item `inc`,`dec`
\item `add`
\item `imul, mul`
\item `sub`
\item `idiv, div`
\item `call, ret`
\item `push, pop`
\enditemize



# Answer




Refer to the second volume of [Intel 64 and IA-32 Architectures Software Developer's Manual].




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```


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From the `_start` label.


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* ring = 0, this is the 0-th protection ring, we are actually in the most privileged mode.


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# Question 46


Read about microcode in general and processor pipelines.


# Answer




Microcode is the program code one level _below_ assembly, that is used to
encode the logic of complex instructions. It is not accessible to programmer
and virtually everything about it is a trade secret of computer manufacturer.

The processor pipeline allows you to execute multiple microcode instructions
at time, if they use different parts of CPU. It is a great performance
booster.

This document contains a good insight on these topics:
[The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and
compiler makers](http://www.agner.org/optimize/microarchitecture.pdf)



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because the latter can be viewed as a particular type of cache.


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fields contain stub zeros.


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[https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html](https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html)


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will see the error message `Segmentation fault`.


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`Bus error`.


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