Digital IC Functionality Duplication using Neural Networks

Reproduce the functional behaviour of small digital sequential circuits with LSTM networks trained on input–output traces — a learned functional digital twin.

Presented at the 2023 IEEE 17th International Conference on Industrial and Information Systems (ICIIS) — open the paper on IEEE Xplore.

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The idea

Digital sequential circuits (counters, shift registers, LFSRs, simple FSMs) are deterministic input → state → output mappings. Train an LSTM on traces collected from the original VHDL/Quartus simulation and you get a learned model that — given the same inputs — reproduces the original circuit's outputs to within an acceptable bit-error rate. A functional digital twin, without re-synthesising the design.

Why a neural net, not a lookup table?

Pure memorisation works for combinational logic but breaks for sequential circuits: the same input can produce different outputs depending on the internal state. LSTMs handle this naturally — they carry context across time steps, which is exactly what counters, shift registers, and FSMs do.

How it's built

  VHDL design ──▶ Quartus / ModelSim sim ──▶ time-aligned I/O traces (.txt)
                                              │
                                              ▼
                                    ┌──────────────────┐
                                    │   LSTM trained   │
                                    │   on input bits  │
                                    │   → output bits  │
                                    └────────┬─────────┘
                                             ▼
                                  Predicted output trace
                                  (compare per-bit vs ground truth)

• Model: LSTM(s), trained per-circuit on I/O traces
• Objective: minimise per-bit sequence error across time steps so combinational and sequential behaviour are reproduced
• Stack: Python · TensorFlow / Keras · Quartus · ModelSim
• Datasets: generated separately — see Sequential Logic Datasets with Designs for VHDL testbenches, schematic files, and the trace-export pipeline

Quickstart

git clone https://github.com/Anjanamb/Digital-IC-Functionality-Duplication-Using-NN.git
cd Digital-IC-Functionality-Duplication-Using-NN

python -m venv venv
source venv/bin/activate            # Linux / macOS
# .\venv\Scripts\Activate.ps1       # Windows

pip install numpy tensorflow keras-tuner wandb flask

Place trace .txt files (generated from the datasets repo) under a top-level data/ folder, then run the training and evaluation scripts inside NN for testing/.

Project structure

Digital-IC-Functionality-Duplication-Using-NN/
├─ Logic_Function/          # VHDL designs, schematics, trace generators
├─ NN for testing/          # LSTM training + evaluation scripts
├─ LICENSE
└─ README.md

Citing this work

@inproceedings{bandara2023digitalic,
  author    = {Bandara, Anjana and others},
  title     = {Digital Integrated Circuit Functionality Duplication Using Neural Networks},
  booktitle = {2023 IEEE 17th International Conference on Industrial and Information Systems (ICIIS)},
  year      = {2023},
  url       = {https://ieeexplore.ieee.org/document/10253575}
}

Replace url with the canonical DOI once you have it from the IEEE Xplore page.

Contributors

• Anjana Bandara (@Anjanamb)
• Ayesh Rajakaruna
• @sahannt98

License

MIT — see anjanamb.github.io for more projects.