AArch64 special register designations Change range of o0 to [0, 3] (#342

)

The documented syntax doesn't allow designation of all possible special
registers (e.g. "ICC_CTLR_EL3" designated with "3:6:12:12:4").

clang supports the documented syntax but not gcc.  

Both compilers support an alternative syntax with <o0> in [0, 3]:
`s<o0>_<o1>_c<CRm>_c<CRn>_<o2>`.

main/acle.md

@@ -419,6 +419,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
 * Unified Function Multi Versioning features memtag and memtag2.
 * Unified Function Multi Versioning features aes and pmull.
 * Unified Function Multi Versioning features sve2-aes and sve2-pmull128.
+* Fixed range of operand `o0` (too small) in AArch64 system register designations.
 
 ### References
 
@@ -5414,7 +5415,7 @@ When specifying a system register to `__arm_rsr`, `__arm_rsr64`, `__arm_rsr128`,
 
 Where:
 
-* `<o0>` is a decimal integer in the range `[0, 1]`
+* `<o0>` is a decimal integer in the range `[0, 3]`
 * `<op1>`, `<op2>` are decimal integers in the range `[0, 7]`
 * `<CRm>`, `<CRn>` are decimal integers in the range `[0, 15]`