Moved again

BOM/66558432.csv

@@ -0,0 +1,9 @@
+"Index","Quantity","Part Number","Manufacturer Part Number","Description","Customer Reference","Backorder","Unit Price","Extended Price"
+"1","1","296-50636-ND","OPA354AIDDAG3","IC OPAMP VFB 1 CIRCUIT 8SOPWRPAD","","0","3.31000","$3.31"
+"2","2","3296W-103LF-ND","3296W-1-103LF","TRIMMER 10K OHM 0.5W PC PIN TOP","","0","3.65000","$7.30"
+"3","1","296-32292-1-ND","SN74LVC1G123DCTT","IC MULTIVIBRATOR 18.5NS SM8","","0","1.58000","$1.58"
+"4","2","296-43611-1-ND","TLV3501AIDR","IC COMP 4.5NS R-R HS 8-SOIC","","0","4.09000","$8.18"
+"5","1","LTC6228HS8#PBF-ND","LTC6228HS8#PBF","IC OPAMP GP 1 CIRCUIT 8SO","","0","7.13000","$7.13"
+"6","1","1568-1123-ND","BOB-13655","SOIC TO DIP ADAPTER 8PIN 1=4 PCS","","0","4.20000","$4.20"
+"7","2","CT94EY104-ND","CT94EY104","TRIMMER 100K OHM 0.5W PC PIN TOP","","0","2.35000","$4.70"
+"","","","","","","","Subtotal","$36.40"

FPGA_firmware/IQviewer.tcl

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+#See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53021.pdf
+#and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii52003.pdf
+
+# run with ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl
+# not quartus_sh
+
+# ~/NAS/primary_a/Projects/fpga/prime/quartus/bin/quartus_stp_tcl -t IQviewer.tcl
+
+proc pause {{message "Hit Enter to continue ==> "}} {
+    puts -nonewline $message
+    flush stdout
+    gets stdin
+}
+
+proc hex_to_signed {value} {
+  set sign [expr {($value & 0b10000000000000000000000000000000)}]
+  set mag  [expr {($value & 0b01111111111111111111111111111111)}]
+  if {$sign==0} {
+    set exp 0
+  } else {
+    set exp [expr -2**31]
+  }
+  set value [expr {$exp + $mag}]
+  return $value
+}
+#thanks Quantum0xE7 on SO!
+
+
+
+
+set usb [lindex [get_hardware_names] 0]
+set device_name [lindex [get_device_names -hardware_name $usb] 0]
+
+start_insystem_source_probe -device_name $device_name -hardware_name $usb
+
+set output_filename "../eppenwolf/runs/phage_experiment_6/fluorescence_slide_1.csv"
+
+array set waveform {}
+
+
+while {1} {
+
+    set previous_count_binary [read_probe_data -instance_index 0];
+    set I_count_binary [read_probe_data -instance_index 0];
+
+    while {$I_count_binary == $previous_count_binary} {
+        puts "Integrating..."
+        after 1000;
+        set I_count_binary [read_probe_data -instance_index 0];
+        set Q_count_binary [read_probe_data -instance_index 1];
+
+    }
+
+    binary scan [binary format B64 [format "%064s" $I_count_binary]] W I_count_binary_scanned
+    binary scan [binary format B64 [format "%064s" $Q_count_binary]] W Q_count_binary_scanned
+
+    set I_count [hex_to_signed $I_count_binary_scanned];
+    set Q_count [hex_to_signed $Q_count_binary_scanned];
+
+    puts $I_count;
+    puts $Q_count;
+
+    puts [expr { sqrt((double($I_count)*double($I_count)) + (double($Q_count)*double($Q_count))) } ];
+    puts [expr {  atan( $Q_count / double($I_count)) }];
+
+    #set addc_bin [read_probe_data -instance_index 1];
+    #binary scan [binary format B64 [format "%064s" $addc_bin]] W addc
+
+    pause;
+
+
+
+}
+
+
+#set value "11111111111111111111111111111111";
+
+
+
+
+#end_interactive_probe;

FPGA_firmware/clocks.sdc

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+create_clock -name "clock_50_mhz" -period 20.0ns [get_ports {clock_50_mhz}]
+create_clock -name "main_clock" -period 5.0ns [get_ports {main_clock}]
+
+create_clock -name "PMT_in" -period 5.0ns [get_ports {PMT_in}]
+create_clock -name "light_source_pin" -period 300ns [get_ports {light_source_pin}]
+
+
+derive_pll_clocks
+derive_clock_uncertainty

FPGA_firmware/fluorescence_FPGA.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 00:35:40  November 05, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		fluorescence_FPGA_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY fluorescence_FPGA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:35:40  NOVEMBER 05, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_location_assignment PIN_D3 -to light_source_pin
+set_location_assignment PIN_R8 -to clock_50_mhz
+set_location_assignment PIN_C3 -to PMT_in
+set_location_assignment PIN_A3 -to pulse_out_pin
+set_location_assignment PIN_A15 -to LEDs[0]
+set_location_assignment PIN_A13 -to LEDs[1]
+set_location_assignment PIN_B13 -to LEDs[2]
+set_location_assignment PIN_A11 -to LEDs[3]
+set_location_assignment PIN_D1 -to LEDs[4]
+set_location_assignment PIN_F3 -to LEDs[5]
+set_location_assignment PIN_B1 -to LEDs[6]
+set_location_assignment PIN_L3 -to LEDs[7]
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name QIP_FILE altsource_probe/synthesis/altsource_probe.qip
+set_global_assignment -name VERILOG_FILE fluorescence_FPGA.v
+set_global_assignment -name SDC_FILE clocks.sdc
+set_global_assignment -name SOURCE_FILE source.spf
+set_global_assignment -name VERILOG_FILE readout.v
+set_global_assignment -name QIP_FILE clkgen.qip
+set_global_assignment -name QIP_FILE ram.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top