Merge pull request #20719 from alexrp/misc-porting

`std.os.linux`: A handful of random porting fixes, mostly for `armeb` and `thumbeb`

Author: andrewrk

lib/std/os/linux.zig

@@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) {
     .x86 => @import("linux/x86.zig"),
     .x86_64 => @import("linux/x86_64.zig"),
     .aarch64, .aarch64_be => @import("linux/arm64.zig"),
-    .arm, .thumb => @import("linux/arm-eabi.zig"),
+    .arm, .armeb, .thumb, .thumbeb => @import("linux/arm-eabi.zig"),
     .riscv64 => @import("linux/riscv64.zig"),
     .sparc64 => @import("linux/sparc64.zig"),
     .mips, .mipsel => @import("linux/mips.zig"),
@@ -103,7 +103,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) {
     .x86 => syscalls.X86,
     .x86_64 => syscalls.X64,
     .aarch64, .aarch64_be => syscalls.Arm64,
-    .arm, .thumb => syscalls.Arm,
+    .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
     .riscv64 => syscalls.RiscV64,
     .sparc64 => syscalls.Sparc64,
     .mips, .mipsel => syscalls.Mips,
@@ -142,7 +142,7 @@ pub const MAP = switch (native_arch) {
         UNINITIALIZED: bool = false,
         _: u5 = 0,
     },
-    .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
+    .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
         TYPE: MAP_TYPE,
         FIXED: bool = false,
         ANONYMOUS: bool = false,
@@ -290,7 +290,7 @@ pub const O = switch (native_arch) {
         TMPFILE: bool = false,
         _: u9 = 0,
     },
-    .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {
+    .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
         ACCMODE: ACCMODE = .RDONLY,
         _2: u4 = 0,
         CREAT: bool = false,
@@ -4787,13 +4787,72 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
 }
 
 pub const MINSIGSTKSZ = switch (native_arch) {
-    .x86, .x86_64, .arm, .mipsel => 2048,
-    .aarch64 => 5120,
+    .arc,
+    .arm,
+    .armeb,
+    .csky,
+    .hexagon,
+    .m68k,
+    .mips,
+    .mipsel,
+    .mips64,
+    .mips64el,
+    .powerpc,
+    .powerpcle,
+    .riscv32,
+    .riscv64,
+    .s390x,
+    .thumb,
+    .thumbeb,
+    .x86,
+    .x86_64,
+    .xtensa,
+    => 2048,
+    .loongarch64,
+    .sparc,
+    .sparcel,
+    .sparc64,
+    => 4096,
+    .aarch64,
+    .aarch64_be,
+    => 5120,
+    .powerpc64,
+    .powerpc64le,
+    => 8192,
     else => @compileError("MINSIGSTKSZ not defined for this architecture"),
 };
 pub const SIGSTKSZ = switch (native_arch) {
-    .x86, .x86_64, .arm, .mipsel => 8192,
-    .aarch64 => 16384,
+    .arc,
+    .arm,
+    .armeb,
+    .csky,
+    .hexagon,
+    .m68k,
+    .mips,
+    .mipsel,
+    .mips64,
+    .mips64el,
+    .powerpc,
+    .powerpcle,
+    .riscv32,
+    .riscv64,
+    .s390x,
+    .thumb,
+    .thumbeb,
+    .x86,
+    .x86_64,
+    .xtensa,
+    => 8192,
+    .aarch64,
+    .aarch64_be,
+    .loongarch64,
+    .sparc,
+    .sparcel,
+    .sparc64,
+    => 16384,
+    .powerpc64,
+    .powerpc64le,
+    => 32768,
     else => @compileError("SIGSTKSZ not defined for this architecture"),
 };
 
@@ -7294,7 +7353,7 @@ pub const AUDIT = struct {
         ARMEB = toAudit(.armeb),
         CSKY = toAudit(.csky),
         HEXAGON = @intFromEnum(std.elf.EM.HEXAGON),
-        X86 = toAudit(.x86),
+        LOONGARCH64 = toAudit(.loongarch64),
         M68K = toAudit(.m68k),
         MIPS = toAudit(.mips),
         MIPSEL = toAudit(.mips) | LE,
@@ -7308,18 +7367,22 @@ pub const AUDIT = struct {
         S390X = toAudit(.s390x),
         SPARC = toAudit(.sparc),
         SPARC64 = toAudit(.sparc64),
+        X86 = toAudit(.x86),
         X86_64 = toAudit(.x86_64),
+        XTENSA = toAudit(.xtensa),
 
         fn toAudit(arch: std.Target.Cpu.Arch) u32 {
             var res: u32 = @intFromEnum(arch.toElfMachine());
             if (arch.endian() == .little) res |= LE;
             switch (arch) {
                 .aarch64,
+                .loongarch64,
                 .mips64,
                 .mips64el,
                 .powerpc64,
                 .powerpc64le,
                 .riscv64,
+                .s390x,
                 .sparc64,
                 .x86_64,
                 => res |= @"64BIT",

lib/std/os/linux/tls.zig

@@ -49,7 +49,23 @@ const TLSVariant = enum {
 };
 
 const tls_variant = switch (native_arch) {
-    .arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => TLSVariant.VariantI,
+    .arm,
+    .armeb,
+    .thumb,
+    .thumbeb,
+    .aarch64,
+    .aarch64_be,
+    .riscv32,
+    .riscv64,
+    .mips,
+    .mipsel,
+    .mips64,
+    .mips64el,
+    .powerpc,
+    .powerpcle,
+    .powerpc64,
+    .powerpc64le,
+    => TLSVariant.VariantI,
     .x86_64, .x86, .sparc64 => TLSVariant.VariantII,
     else => @compileError("undefined tls_variant for this architecture"),
 };
@@ -58,27 +74,27 @@ const tls_variant = switch (native_arch) {
 const tls_tcb_size = switch (native_arch) {
     // ARM EABI mandates enough space for two pointers: the first one points to
     // the DTV while the second one is unspecified but reserved
-    .arm, .armeb, .thumb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
+    .arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
     // One pointer-sized word that points either to the DTV or the TCB itself
     else => @sizeOf(usize),
 };
 
 // Controls if the TP points to the end of the TCB instead of its beginning
 const tls_tp_points_past_tcb = switch (native_arch) {
-    .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => true,
+    .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => true,
     else => false,
 };
 
 // Some architectures add some offset to the tp and dtv addresses in order to
 // make the generated code more efficient
 
 const tls_tp_offset = switch (native_arch) {
-    .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x7000,
+    .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x7000,
     else => 0,
 };
 
 const tls_dtv_offset = switch (native_arch) {
-    .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x8000,
+    .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x8000,
     .riscv32, .riscv64 => 0x800,
     else => 0,
 };
@@ -150,7 +166,7 @@ pub fn setThreadPointer(addr: usize) void {
                 : [addr] "r" (addr),
             );
         },
-        .arm, .thumb => {
+        .arm, .armeb, .thumb, .thumbeb => {
             const rc = @call(.always_inline, linux.syscall1, .{ .set_tls, addr });
             assert(rc == 0);
         },