x86_64: support more non-sse movement options

Also improve abi compatibility.

Closes #23426

Author: jacobly0

src/arch/x86_64/CodeGen.zig

@@ -110436,11 +110436,12 @@ fn allocRegOrMemAdvanced(self: *CodeGen, ty: Type, inst: ?Air.Inst.Index, reg_ok
     if (reg_ok) need_mem: {
         if (std.math.isPowerOfTwo(abi_size) and abi_size <= @as(u32, max_abi_size: switch (ty.zigTypeTag(zcu)) {
             .float => switch (ty.floatBits(self.target.*)) {
-                16, 32, 64, 128 => 16,
+                16, 32, 64, 128 => if (self.hasFeature(.sse)) 16 else break :need_mem,
                 80 => break :need_mem,
                 else => unreachable,
             },
             .vector => {
+                if (!self.hasFeature(.sse)) break :need_mem;
                 const elem_ty = ty.childType(zcu);
                 break :max_abi_size if (elem_ty.toIntern() == .bool_type)
                     8
@@ -110467,16 +110468,16 @@ fn regClassForType(self: *CodeGen, ty: Type) Register.Class {
     const zcu = pt.zcu;
     if (self.floatBits(ty)) |float_bits| return switch (float_bits) {
         80 => .x87,
-        else => .sse,
+        else => if (self.hasFeature(.sse)) .sse else .general_purpose,
     };
     if (!ty.isVector(zcu)) return .general_purpose;
     const elem_ty = ty.childType(zcu);
     return if (elem_ty.toIntern() == .bool_type)
         .general_purpose
     else if (self.floatBits(elem_ty)) |float_bits|
-        if (float_bits == 80) .x87 else .sse
+        if (float_bits == 80) .x87 else if (self.hasFeature(.sse)) .sse else .general_purpose
     else if (self.intInfo(elem_ty)) |_|
-        .sse
+        if (self.hasFeature(.sse)) .sse else .general_purpose
     else
         .general_purpose;
 }
@@ -123265,6 +123266,33 @@ fn genCopy(self: *CodeGen, ty: Type, dst_mcv: MCValue, src_mcv: MCValue, opts: C
                 .register => |src_reg| switch (dst_regs[0].class()) {
                     .general_purpose => switch (src_reg.class()) {
                         else => unreachable,
+                        .x87 => {
+                            assert(dst_regs.len == 2);
+                            const frame_index = try self.allocFrameIndex(.initType(ty, pt.zcu));
+                            if (self.register_manager.isKnownRegFree(.st7)) {
+                                try self.asmRegister(.{ .f_, .ld }, src_reg);
+                                try self.asmMemory(.{ .f_p, .st }, .{
+                                    .base = .{ .frame = frame_index },
+                                    .mod = .{ .rm = .{ .size = .tbyte } },
+                                });
+                            } else {
+                                try self.asmRegister(.{ .f_, .xch }, src_reg);
+                                try self.asmMemory(.{ .f_p, .st }, .{
+                                    .base = .{ .frame = frame_index },
+                                    .mod = .{ .rm = .{ .size = .tbyte } },
+                                });
+                                try self.asmMemory(.{ .f_, .ld }, .{
+                                    .base = .{ .frame = frame_index },
+                                    .mod = .{ .rm = .{ .size = .tbyte } },
+                                });
+                                try self.asmRegister(.{ .f_, .xch }, src_reg);
+                            }
+                            for (dst_regs, 0..) |dst_reg, dst_index| try self.asmRegisterMemory(.{ ._, .mov }, dst_reg.to64(), .{
+                                .base = .{ .frame = frame_index },
+                                .mod = .{ .rm = .{ .size = .qword, .disp = @intCast(8 * dst_index) } },
+                            });
+                            return;
+                        },
                         .sse => if (ty.abiSize(pt.zcu) <= 16) {
                             if (self.hasFeature(.avx)) {
                                 try self.asmRegisterRegister(.{ .v_q, .mov }, dst_regs[0].to64(), src_reg.to128());
@@ -124177,13 +124205,29 @@ fn genInlineMemcpy(self: *CodeGen, dst_ptr: MCValue, src_ptr: MCValue, len: MCVa
                     try self.asmMemoryRegister(.{ ._ps, .movu }, try dst_ptr.deref().mem(self, .{ .size = .xword }), reg.to128());
                     return;
                 }
+            } else {
+                if (self.register_manager.tryAllocReg(null, abi.RegisterClass.gp)) |reg| {
+                    for (0..2) |limb_index| {
+                        try self.asmRegisterMemory(.{ ._, .mov }, reg.to64(), try src_ptr.deref().mem(self, .{ .size = .qword, .disp = @intCast(8 * limb_index) }));
+                        try self.asmMemoryRegister(.{ ._, .mov }, try dst_ptr.deref().mem(self, .{ .size = .qword, .disp = @intCast(8 * limb_index) }), reg.to64());
+                    }
+                    return;
+                }
             },
             32 => if (self.hasFeature(.avx)) {
                 if (self.register_manager.tryAllocReg(null, abi.RegisterClass.sse)) |reg| {
                     try self.asmRegisterMemory(.{ .v_dqu, .mov }, reg.to256(), try src_ptr.deref().mem(self, .{ .size = .yword }));
                     try self.asmMemoryRegister(.{ .v_dqu, .mov }, try dst_ptr.deref().mem(self, .{ .size = .yword }), reg.to256());
                     return;
                 }
+            } else {
+                if (self.register_manager.tryAllocReg(null, abi.RegisterClass.gp)) |reg| {
+                    for (0..4) |limb_index| {
+                        try self.asmRegisterMemory(.{ ._, .mov }, reg.to64(), try src_ptr.deref().mem(self, .{ .size = .qword, .disp = @intCast(8 * limb_index) }));
+                        try self.asmMemoryRegister(.{ ._, .mov }, try dst_ptr.deref().mem(self, .{ .size = .qword, .disp = @intCast(8 * limb_index) }), reg.to64());
+                    }
+                    return;
+                }
             },
         },
     };

src/arch/x86_64/abi.zig

@@ -148,38 +148,64 @@ pub fn classifySystemV(ty: Type, zcu: *Zcu, target: *const std.Target, ctx: Cont
             result[0] = .integer;
             return result;
         },
-        .float => switch (ty.floatBits(target.*)) {
+        .float => if (std.Target.x86.featureSetHas(target.cpu.features, .soft_float)) {
+            @memset(result[0 .. std.math.divCeil(u16, ty.floatBits(target.*), 64) catch unreachable], .integer);
+            return result;
+        } else switch (ty.floatBits(target.*)) {
             16 => {
-                if (ctx == .field) {
-                    result[0] = .memory;
-                } else {
+                result[0] = if (ctx == .field)
+                    .memory
+                else if (std.Target.x86.featureSetHasAll(target.cpu.features, .{ .sse, .sse2 }))
                     // TODO clang doesn't allow __fp16 as .ret or .arg
-                    result[0] = .sse;
-                }
+                    .sse
+                else
+                    .integer;
                 return result;
             },
             32 => {
-                result[0] = .float;
+                if (std.Target.x86.featureSetHas(target.cpu.features, .sse)) {
+                    result[0] = .float;
+                } else if (std.Target.x86.featureSetHas(target.cpu.features, .x87)) {
+                    result[0] = .x87;
+                    result[1] = .x87up;
+                } else {
+                    @memset(result[0..2], .integer);
+                }
                 return result;
             },
             64 => {
-                result[0] = .sse;
+                if (std.Target.x86.featureSetHas(target.cpu.features, .sse2)) {
+                    result[0] = .sse;
+                } else if (std.Target.x86.featureSetHas(target.cpu.features, .x87)) {
+                    result[0] = .x87;
+                    result[1] = .x87up;
+                } else {
+                    @memset(result[0..2], .integer);
+                }
                 return result;
             },
             128 => {
-                // "Arguments of types __float128, _Decimal128 and __m128 are
-                // split into two halves.  The least significant ones belong
-                // to class SSE, the most significant one to class SSEUP."
-                result[0] = .sse;
-                result[1] = .sseup;
+                if (std.Target.x86.featureSetHas(target.cpu.features, .sse)) {
+                    // "Arguments of types __float128, _Decimal128 and __m128 are
+                    // split into two halves.  The least significant ones belong
+                    // to class SSE, the most significant one to class SSEUP."
+                    result[0] = .sse;
+                    result[1] = .sseup;
+                } else {
+                    @memset(result[0..2], .integer);
+                }
                 return result;
             },
             80 => {
-                // "The 64-bit mantissa of arguments of type long double
-                // belongs to classX87, the 16-bit exponent plus 6 bytes
-                // of padding belongs to class X87UP."
-                result[0] = .x87;
-                result[1] = .x87up;
+                if (std.Target.x86.featureSetHas(target.cpu.features, .x87)) {
+                    // "The 64-bit mantissa of arguments of type long double
+                    // belongs to classX87, the 16-bit exponent plus 6 bytes
+                    // of padding belongs to class X87UP."
+                    result[0] = .x87;
+                    result[1] = .x87up;
+                } else {
+                    @memset(result[0..2], .integer);
+                }
                 return result;
             },
             else => unreachable,