Merge pull request #20708 from alexrp/target-cleanup-2

`std.Target`: Remove more dead architecture tags.

Author: andrewrk

lib/compiler/aro/aro/target.zig

@@ -17,8 +17,6 @@ pub fn intMaxType(target: std.Target) Type {
         .riscv64,
         .powerpc64,
         .powerpc64le,
-        .tce,
-        .tcele,
         .ve,
         => return .{ .specifier = .long },
 
@@ -54,8 +52,6 @@ pub fn intPtrType(target: std.Target) Type {
         .riscv32,
         .xcore,
         .hexagon,
-        .tce,
-        .tcele,
         .m68k,
         .spir,
         .spirv32,
@@ -153,7 +149,7 @@ pub fn isTlsSupported(target: std.Target) bool {
         return supported;
     }
     return switch (target.cpu.arch) {
-        .tce, .tcele, .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
+        .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
         else => true,
     };
 }
@@ -470,25 +466,18 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .mipsel,
         .powerpc,
         .powerpcle,
-        .r600,
         .riscv32,
         .sparc,
         .sparcel,
-        .tce,
-        .tcele,
         .thumb,
         .thumbeb,
         .x86,
         .xcore,
         .nvptx,
-        .amdil,
-        .hsail,
         .spir,
         .kalimba,
-        .shave,
         .lanai,
         .wasm32,
-        .renderscript32,
         .aarch64_32,
         .spirv32,
         .loongarch32,
@@ -498,13 +487,10 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
 
         .aarch64 => copy.cpu.arch = .arm,
         .aarch64_be => copy.cpu.arch = .armeb,
-        .amdil64 => copy.cpu.arch = .amdil,
         .nvptx64 => copy.cpu.arch = .nvptx,
         .wasm64 => copy.cpu.arch = .wasm32,
-        .hsail64 => copy.cpu.arch = .hsail,
         .spir64 => copy.cpu.arch = .spir,
         .spirv64 => copy.cpu.arch = .spirv32,
-        .renderscript64 => copy.cpu.arch = .renderscript32,
         .loongarch64 => copy.cpu.arch = .loongarch32,
         .mips64 => copy.cpu.arch = .mips,
         .mips64el => copy.cpu.arch = .mipsel,
@@ -529,12 +515,8 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .r600,
-        .shave,
         .sparcel,
         .spu_2,
-        .tce,
-        .tcele,
         .xcore,
         .xtensa,
         => return null,
@@ -544,13 +526,10 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .amdgcn,
         .bpfeb,
         .bpfel,
-        .amdil64,
         .nvptx64,
         .wasm64,
-        .hsail64,
         .spir64,
         .spirv64,
-        .renderscript64,
         .loongarch64,
         .mips64,
         .mips64el,
@@ -564,17 +543,14 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         => {}, // Already 64 bit
 
         .aarch64_32 => copy.cpu.arch = .aarch64,
-        .amdil => copy.cpu.arch = .amdil64,
         .arm => copy.cpu.arch = .aarch64,
         .armeb => copy.cpu.arch = .aarch64_be,
-        .hsail => copy.cpu.arch = .hsail64,
         .loongarch32 => copy.cpu.arch = .loongarch64,
         .mips => copy.cpu.arch = .mips64,
         .mipsel => copy.cpu.arch = .mips64el,
         .nvptx => copy.cpu.arch = .nvptx64,
         .powerpc => copy.cpu.arch = .powerpc64,
         .powerpcle => copy.cpu.arch = .powerpc64le,
-        .renderscript32 => copy.cpu.arch = .renderscript64,
         .riscv32 => copy.cpu.arch = .riscv64,
         .sparc => copy.cpu.arch = .sparc64,
         .spir => copy.cpu.arch = .spir64,
@@ -620,16 +596,13 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .powerpcle => "powerpcle",
         .powerpc64 => "powerpc64",
         .powerpc64le => "powerpc64le",
-        .r600 => "r600",
         .amdgcn => "amdgcn",
         .riscv32 => "riscv32",
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
         .sparcel => "sparcel",
         .s390x => "s390x",
-        .tce => "tce",
-        .tcele => "tcele",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
         .x86 => "i386",
@@ -638,21 +611,14 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .amdil => "amdil",
-        .amdil64 => "amdil64",
-        .hsail => "hsail",
-        .hsail64 => "hsail64",
         .spir => "spir",
         .spir64 => "spir64",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
-        .shave => "shave",
         .lanai => "lanai",
         .wasm32 => "wasm32",
         .wasm64 => "wasm64",
-        .renderscript32 => "renderscript32",
-        .renderscript64 => "renderscript64",
         .ve => "ve",
         // Note: spu_2 is not supported in LLVM; this is the Zig arch name
         .spu_2 => "spu_2",
@@ -668,7 +634,7 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .freebsd => "freebsd",
         .fuchsia => "fuchsia",
         .linux => "linux",
-        .lv2 => "lv2",
+        .ps3 => "lv2",
         .netbsd => "netbsd",
         .openbsd => "openbsd",
         .solaris => "solaris",