soc: infineon: cat1b: psc3: noinit linker update

This device needs a custom noinit.ld file to account
for how ROM uses RAM during boot.

Signed-off-by: Bill Waters <[email protected]>

Author: billwatersiii

soc/infineon/cat1b/psc3/CMakeLists.txt

@@ -3,6 +3,7 @@
 
 zephyr_sources(soc.c)
 zephyr_include_directories(.)
+zephyr_linker_sources(NOINIT noinit.ld)
 
 # CAT1B family defines
 zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)

soc/infineon/cat1b/psc3/Kconfig

@@ -28,3 +28,4 @@ config SOC_SERIES_PSC3
 	select CPU_CORTEX_M_HAS_CMSE
 	select SOC_EARLY_INIT_HOOK
 	select CPU_CORTEX_M33
+	select NOINIT_SNIPPET_FIRST

soc/infineon/cat1b/psc3/noinit.ld

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* The boot ROM in this device uses the first 8k of SRAM while running.  Applications like
+ * tests\drivers\watchdog\wdt_basic_api expect that variables placed in noint memory will retain
+ * there value through a reset.  This means that the noinit memory region must be located after
+ * the first 8k of SRAM.  The line below is added to the noinit linker section to ensure that.
+ * It must be used in conjunction with the NOINIT_SNIPPET_FIRST configuration option that has
+ * been added to the Kconfig file.
+ */
+. = MAX(ABSOLUTE(.), 0x34002000);