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boards: nxp: imx95_evk_15x15: add i.MX 95 15x15 LPDDR4x EVK variant
Add initial support for i.MX 95 15x15 LPDDR4x EVK board. This board uses the i.MX 95 15x15 SoC that shares many similarities to the already supported i.MX 95 19x19 SoC used for the i.MX 95 19x19 LPDDR5 EVK. This enables Zephyr to boot and run on the i.MX 95 15x15 EVK and provides a foundation for further peripheral enablement and application development. Signed-off-by: Aziz Sellami <[email protected]>
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‎boards/nxp/imx95_evk_15x15/Kconfig.imx95_evk_15x15

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_IMX95_EVK_15X15
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select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_15X15_MIMX9596_A55
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select SOC_PART_NUMBER_MIMX9596AVTXN

‎boards/nxp/imx95_evk_15x15/board.yml

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board:
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name: imx95_evk_15x15
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full_name: i.MX95 15x15 EVK
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vendor: nxp
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socs:
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- name: mimx9596

‎boards/nxp/imx95_evk_15x15/doc/index.rst

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.. zephyr:board:: imx95_evk_15x15
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Overview
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********
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The i.MX95 EVK (IMX95LP4XEVK-15) board is a platform designed to show the
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most commonly used features of the i.MX 95 applications processor.
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It is an entry-level development board, which helps developers to get familiar
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with the processor before investing a large amount of resources in more
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specific designs. The i.MX 95 device on the board comes in a compact
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15 x 15 mm package.
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Hardware
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********
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- i.MX 95 applications processor
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- The processor integrates up to six Arm Cortex-A55 cores, and supports
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functional safety with built-in Arm Cortex-M33 and -M7 cores
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- DRAM memory: 8-Gbit LPDDR4x DRAM
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- eMMC: 64 GB Micron eMMC
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- USB interface: Two USB ports: Type-A and Type-C
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- Audio codec interface
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- One audio codec WM8962B
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- One 3.5 mm 4-pole CTIA standard audio jack
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- One 4-pin connector to connect speaker
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- Ethernet interface
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- ENET2 controller
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- Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
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connector connected with an external PHY, RTL8211
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- ENET1 controller
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- Supports 100 Mbit/s or 1000 Mbit/s RGMII Ethernet with one RJ45
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connector connected with an external PHY, RTL8211
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- M.2 interface: One Wi-Fi/Bluetooth Murata Type-2EL module based on NXP AW612
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chip supporting 1x1 Wi-Fi 6 and Bluetooth 5.3
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- MIPI CSI interface: Connects to one 22-pin or 36-pin miniSAS connector using x4 lane
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configuration
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- MIPI CSIDSI interface: Connects to one 36-pin miniSAS connector using x4 lane
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configuration
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- LVDS interface: two mini-SAS connectors each with x4-lane configuration
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- CAN interface: One 4-pin CAN headers for external connection
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- SD card interface: one 4-bit SD3.0 microSD card
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- I2C interface: I2C1 to I2C6 controllers
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- FT4232H I2C interface: PCT2075 temperature sensor and current monitoring devices
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- ADC interface: two 4-channel ADC header
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- Debug interface
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- One USB-to-UART/MPSSE device, FT4232H
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- One USB 2.0 Type-C connector (J31) for FT4232H provides quad serial ports
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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System Clock
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------------
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This board configuration uses a system clock frequency of 24 MHz for Cortex-A55.
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Cortex-A55 Core runs up to 1.8 GHz.
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Serial Port
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-----------
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This board configuration uses a single serial communication channel with the
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CPU's UART1 for Cortex-A55.
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Programming and Debugging (A55)
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*******************************
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Use this configuration to run basic Zephyr applications and kernel tests,
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for example, with the :zephyr:code-sample:`synchronization` sample:
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1. Build and run the Non-SMP application
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: imx95_evk_15x15/mimx9596/a55
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:goals: build
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This will build an image (zephyr.bin) with the synchronization sample app.
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Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
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plug the SD card into the board. Power it up and stop the u-boot execution at
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prompt.
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Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
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.. code-block:: console
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fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
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Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
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.. code-block:: console
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fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
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It will display the following console output:
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.. code-block:: console
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*** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 ***
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thread_a: Hello World from cpu 0 on imx95_evk_15x15!
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thread_b: Hello World from cpu 0 on imx95_evk_15x15!
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thread_a: Hello World from cpu 0 on imx95_evk_15x15!
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thread_b: Hello World from cpu 0 on imx95_evk_15x15!
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thread_a: Hello World from cpu 0 on imx95_evk_15x15!
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.. _System Control and Management Interface (SCMI):
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https://developer.arm.com/documentation/den0056/latest/
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.. _i.MX Linux BSP release:
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https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX
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.. _MCUX SDK release:
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https://mcuxpresso.nxp.com/
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References
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==========
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More information can refer to NXP official website:
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`NXP website`_.
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.. _NXP website:
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https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95

‎boards/nxp/imx95_evk_15x15/imx95_evk_15x15-pinctrl.dtsi

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx/mimx9596cvtxn-pinctrl.dtsi>
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&pinctrl {
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lpuart1_default: lpuart1_default {
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group0 {
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pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
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<&iomuxc_uart1_txd_lpuart_tx_lpuart1_tx>;
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bias-pull-up;
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slew-rate = "slightly_fast";
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drive-strength = "x4";
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};
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};
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lpuart3_default: lpuart3_default {
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group0 {
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pinmux = <&iomuxc_gpio_io15_lpuart_rx_lpuart3_rx>,
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<&iomuxc_gpio_io14_lpuart_tx_lpuart3_tx>;
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bias-pull-up;
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slew-rate = "slightly_fast";
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drive-strength = "x4";
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};
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};
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};

‎boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.dts

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_mimx95_a55.dtsi>
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#include "imx95_evk_15x15-pinctrl.dtsi"
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/ {
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model = "NXP i.MX95 15x15 A55";
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compatible = "fsl,mimx95";
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chosen {
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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/* sram node actually locates at DDR DRAM */
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zephyr,sram = &dram;
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};
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cpus {
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cpu@0 {
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status = "disabled";
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};
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cpu@100 {
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status = "disabled";
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};
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cpu@200 {
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status = "disabled";
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};
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cpu@300 {
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status = "disabled";
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};
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cpu@400 {
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status = "disabled";
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};
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};
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dram: memory@d0000000 {
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reg = <0xd0000000 DT_SIZE_M(1)>;
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};
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};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&lpuart1_default>;
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pinctrl-names = "default";
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};

‎boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55.yaml

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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identifier: imx95_evk_15x15/mimx9596/a55
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name: NXP i.MX95 15x15 EVK A55
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type: mcu
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arch: arm64
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toolchain:
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- zephyr
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- cross-compile
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ram: 1024
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supported:
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- uart
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- counter
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vendor: nxp

‎boards/nxp/imx95_evk_15x15/imx95_evk_15x15_mimx9596_a55_defconfig

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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# ARM Options
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CONFIG_AARCH64_IMAGE_HEADER=y
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CONFIG_ARMV8_A_NS=y
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# MMU Options
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CONFIG_MAX_XLAT_TABLES=64
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# Cache Options
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_DCACHE_LINE_SIZE_DETECT=y
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CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# Enable Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_MBOX=y
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CONFIG_ARM_SCMI=y
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CONFIG_INTC_INIT_PRIORITY=2
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CONFIG_MBOX_INIT_PRIORITY=3

‎soc/nxp/imx/imx9/imx95/Kconfig.soc

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config SOC
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default "mimx9596" if SOC_MIMX9596
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config SOC_PART_NUMBER_MIMX9596AVTXN
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bool
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config SOC_PART_NUMBER_MIMX9596AVZXN
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bool
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config SOC_PART_NUMBER
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default "MIMX9596AVTXN" if SOC_PART_NUMBER_MIMX9596AVTXN
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default "MIMX9596AVZXN" if SOC_PART_NUMBER_MIMX9596AVZXN

‎west.yml

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groups:
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- hal
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- name: hal_nxp
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revision: d0e49d63ac74208e183ed47ebb4bf8d490ab63fb
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revision: cebb23d4912114df0f1ca356df5bdb1c079dd82f
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path: modules/hal/nxp
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groups:
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- hal

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