gpio: mcux_rgpio: Support IRQ output select and access checks for i.MX95 M7

Support for selecting the IRQ output via the `irq-output-select` property
in devicetree. Updates interrupt configuration and ISR logic to use the
selected IRQ index. For i.MX95 M7, ensures pins and IRQs are configured
only when secure access is allowed by checking PCNS and ICNS registers.

Signed-off-by: Peter van der Perk <[email protected]>

Author: PetervdPerk-NXP

drivers/gpio/gpio_mcux_rgpio.c

@@ -35,6 +35,7 @@ struct mcux_rgpio_config {
 
 	const struct pinctrl_soc_pinmux *pin_muxes;
 	uint8_t mux_count;
+	uint8_t irq_sel;
 };
 
 struct mcux_rgpio_data {
@@ -144,6 +145,14 @@ static int mcux_rgpio_configure(const struct device *dev,
 	}
 #endif
 
+#if defined(CONFIG_SOC_MIMX9596_M7)
+	base->PCNS &= ~BIT(pin);
+	if (base->PCNS & BIT(pin)) {
+		/* We don't have access to this pin */
+		return -ENOTSUP;
+	}
+#endif
+
 	memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg));
 	/* cfg register will be set by pinctrl_configure_pins */
 	pin_cfg.pin_ctrl_flags = reg;
@@ -226,12 +235,20 @@ static int mcux_rgpio_pin_interrupt_configure(const struct device *dev,
 	unsigned int key;
 	uint8_t irqs, irqc;
 
+#if defined(CONFIG_SOC_MIMX9596_M7)
+	base->ICNS &= ~BIT(config->irq_sel);
+	if (base->ICNS & BIT(config->irq_sel)) {
+		/* We don't have access to this IRQ */
+		return -ENOTSUP;
+	}
+#endif
+
 	/* Make sure pin is supported */
 	if ((config->common.port_pin_mask & BIT(pin)) == 0) {
 		return -ENOTSUP;
 	}
 
-	irqs = 0; /* only irq0 is used for irq */
+	irqs = config->irq_sel;
 
 	if (mode == GPIO_INT_MODE_DISABLED) {
 		irqc = kRGPIO_InterruptOrDMADisabled;
@@ -277,9 +294,9 @@ static void mcux_rgpio_port_isr(const struct device *dev)
 	struct mcux_rgpio_data *data = dev->data;
 	uint32_t int_flags;
 
-	int_flags = base->ISFR[0]; /* Notice: only irq0 is used for now */
+	int_flags = base->ISFR[config->irq_sel];
 	int_flags &= config->common.port_pin_mask; /* don't handle unusable pin */
-	base->ISFR[0] = int_flags;
+	base->ISFR[config->irq_sel] = int_flags;
 
 	gpio_fire_callbacks(&data->callbacks, dev, int_flags);
 }
@@ -303,7 +320,8 @@ static DEVICE_API(gpio, mcux_rgpio_driver_api) = {
 	};
 #define MCUX_RGPIO_PIN_INIT(n)							\
 	.pin_muxes = mcux_rgpio_pinmux_##n,					\
-	.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux),
+	.mux_count = DT_PROP_LEN(DT_DRV_INST(n), pinmux),   \
+	.irq_sel   = DT_INST_PROP(n, irq_output_select)     \
 
 #define MCUX_RGPIO_IRQ_INIT(n, i)					\
 	do {								\
@@ -317,6 +335,8 @@ static DEVICE_API(gpio, mcux_rgpio_driver_api) = {
 
 #define MCUX_RGPIO_INIT(n)						\
 	MCUX_RGPIO_PIN_DECLARE(n)					\
+	BUILD_ASSERT((DT_INST_PROP(n, irq_output_select) != 1) || DT_INST_IRQ_HAS_IDX(n, 1),       \
+		     "irq-output-select=1 but IRQ 1 is not defined");                              \
 	static int mcux_rgpio_##n##_init(const struct device *dev);	\
 									\
 	static const struct mcux_rgpio_config mcux_rgpio_##n##_config = { \
@@ -343,12 +363,7 @@ static DEVICE_API(gpio, mcux_rgpio_driver_api) = {
 	{								\
 		DEVICE_MMIO_NAMED_MAP(dev, reg_base, \
 			K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); \
-		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),			\
-		   (MCUX_RGPIO_IRQ_INIT(n, 0);))		\
-									\
-		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1),			\
-			   (MCUX_RGPIO_IRQ_INIT(n, 1);))		\
-									\
+		MCUX_RGPIO_IRQ_INIT(n, DT_INST_PROP(n, irq_output_select));		\
 		return 0;						\
 	}
 

dts/bindings/gpio/nxp,imx-rgpio.yaml

@@ -23,6 +23,17 @@ properties:
   "#gpio-cells":
     const: 2
 
+  irq-output-select:
+    type: int
+    default: 0
+    description: |
+      Select which IRQ line the GPIO controller outputs to.
+      0 = First IRQ line (default)
+      1 = Second IRQ line
+    enum:
+      - 0
+      - 1
+
 gpio-cells:
   - pin
   - flags