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samples: mspi_flash: add support for some boards
this commit enables building and running the sample on stm32h573i_dk board,stm32h735g_disco board, arduino_giga_r1 board, and b_u585i_iot02a board by providing the required overlay and configuration updates. Signed-off-by: Sara Touqan <[email protected]> Signed-off-by: Sarah Younis <[email protected]> Signed-off-by: Mohammad Odeh <[email protected]>
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‎samples/drivers/mspi/mspi_flash/boards/arduino_giga_r1_stm32h747xx_m7.conf‎

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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_LOG=y
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CONFIG_MSPI_LOG_LEVEL_INF=y
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CONFIG_USB_DEVICE_STACK=y
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CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y
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CONFIG_LOG_MODE_DEFERRED=y
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CONFIG_USB_CDC_ACM=y

‎samples/drivers/mspi/mspi_flash/boards/arduino_giga_r1_stm32h747xx_m7.overlay‎

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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Replace the quadspi by a "st,stm32-qspi-controller" compatible */
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/delete-node/ &n25q128a1;
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/ {
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chosen {
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zephyr,console = &cdc_acm_uart0;
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zephyr,shell-uart = &cdc_acm_uart0;
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zephyr,uart-mcumgr = &cdc_acm_uart0;
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};
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aliases {
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/* The sample gets the DT_ALIAS(flash0) as the mspi device */
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flash0 = &n25q128a;
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};
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qspi_memory: qspi-memory@90000000 {
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compatible = "zephyr,memory-region";
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device_type = "memory";
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reg = <0x90000000 DT_SIZE_M(256)>;
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zephyr,memory-region = "QSPI";
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zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_FLASH)>;
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};
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};
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&usbotg_fs {
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status = "okay";
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pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
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pinctrl-names = "default";
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cdc_acm_uart0: cdc_acm_uart0 {
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status = "okay";
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compatible = "zephyr,cdc-acm-uart";
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};
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};
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&cdc_acm_uart0 {
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status = "okay";
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};
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&quadspi {
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compatible = "st,stm32-qspi-controller";
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reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
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interrupts = <92 0>;
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clocks = <&rcc STM32_CLOCK(AHB3, 14U)>;
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clock-names = "qspix";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <DT_FREQ_M(25)>;
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op-mode = "MSPI_CONTROLLER";
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duplex = "MSPI_HALF_DUPLEX";
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status = "okay";
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pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
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&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
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&quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pf6>;
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pinctrl-names = "default";
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n25q128a: qspi-nor-flash@0 {
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compatible = "jedec,mspi-nor";
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reg = <0>;
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size = <DT_SIZE_M(128)>; /* 128 Mbits */
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status = "okay";
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mspi-max-frequency = <DT_FREQ_M(25)>;
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mspi-io-mode = "MSPI_IO_MODE_SINGLE";
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mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
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mspi-hardware-ce-num = <0>;
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read-command = <0x0b>;
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write-command = <0x02>;
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command-length = "INSTR_1_BYTE";
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address-length = "ADDR_3_BYTE";
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rx-dummy = <8>;
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tx-dummy = <0>;
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jedec-id = [1f 89 01];
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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slot1_partition: partition@0 {
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label = "image-1";
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reg = <0x00000000 DT_SIZE_M(1)>;
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};
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storage_partition: partition@100000 {
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label = "storage";
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reg = <0x00100000 DT_SIZE_M(15)>;
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};
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};
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};
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};

‎samples/drivers/mspi/mspi_flash/boards/b_u585i_iot02a.conf‎

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CONFIG_LOG=y
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CONFIG_MSPI_LOG_LEVEL_INF=y

‎samples/drivers/mspi/mspi_flash/boards/b_u585i_iot02a.overlay‎

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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Replace the octospi2 by a "st,stm32-ospi-controller" compatible */
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/delete-node/ &octospi2;
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/ {
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aliases {
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/* The sample gets the DT_ALIAS(flash0) as the mspi device */
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flash0 = &mx25lm51245;
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};
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soc {
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octospi2: spi@420d2400 {
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compatible = "st,stm32-ospi-controller";
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reg = <0x420d2400 0x400>, <0x70000000 DT_SIZE_M(256)>;
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interrupts = <120 0>;
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clock-names = "ospix", "ospi-ker", "ospi-mgr";
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clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>,
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<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
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<&rcc STM32_CLOCK(AHB2, 21)>;
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#address-cells = <1>;
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#size-cells = <0>;
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op-mode = "MSPI_OP_MODE_CONTROLLER";
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status = "okay";
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pinctrl-0 = <&octospim_p2_clk_pf4 &octospim_p2_ncs_pi5
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&octospim_p2_io0_pf0 &octospim_p2_io1_pf1
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&octospim_p2_io2_pf2 &octospim_p2_io3_pf3
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&octospim_p2_io4_ph9 &octospim_p2_io5_ph10
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&octospim_p2_io6_ph11 &octospim_p2_io7_ph12
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&octospim_p2_dqs_pf12>;
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pinctrl-names = "default";
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dmas = <&gpdma1 12 41 0x10480>; /* request 41 for OCTOSPI2 */
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dma-names = "tx_rx";
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mx25lm51245: ospi-nor-flash@0 {
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compatible = "jedec,mspi-nor";
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reg = <0>;
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size = <DT_SIZE_M(512)>; /* 512 Megabits */
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mspi-max-frequency = <DT_FREQ_M(50)>;
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status = "okay";
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mspi-io-mode = "MSPI_IO_MODE_OCTAL";
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mspi-data-rate = "MSPI_DATA_RATE_DUAL"; /* as first step */
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mspi-hardware-ce-num = <0>;
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read-command = <0xEE11>; /* ReaD 4Bytes */
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command-length = "INSTR_2_BYTE";
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write-command = <0x12ED>; /* WRite 4Bytes */
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rx-dummy = <20>;
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jedec-id = [c2 85 3a];
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "nor";
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reg = <0x00000000 DT_SIZE_M(4)>;
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};
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};
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};
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};
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};
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};

‎samples/drivers/mspi/mspi_flash/boards/stm32h573i_dk.conf‎

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CONFIG_LOG=y
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CONFIG_MSPI_LOG_LEVEL_INF=y
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CONFIG_HEAP_MEM_POOL_SIZE=8192

‎samples/drivers/mspi/mspi_flash/boards/stm32h573i_dk.overlay‎

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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Replace the xspi1 by a "st,stm32-mspi-controller" compatible */
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/delete-node/ &xspi1;
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/ {
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aliases {
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/* The sample gets the DT_ALIAS(flash0) as the mspi device */
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flash0 = &mx25lm51245;
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};
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soc {
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xspi1: mspi@47001400 {
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compatible = "st,stm32-xspi-controller";
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reg = <0x47001400 0x400>, <0x90000000 DT_SIZE_M(256)>;
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interrupts = <78 0>;
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clock-names = "xspix", "xspi-ker";
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clocks = <&rcc STM32_CLOCK(AHB4, 20U)>,
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<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <0x17d7840>;
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op-mode = "MSPI_CONTROLLER";
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status = "okay";
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pinctrl-0 = <&octospi1_io0_pb1 &octospi1_io1_pd12
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&octospi1_io2_pc2 &octospi1_io3_pd13
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&octospi1_io4_ph2 &octospi1_io5_ph3
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&octospi1_io6_pg9 &octospi1_io7_pc0
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&octospi1_clk_pf10 &octospi1_ncs_pg6
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&octospi1_dqs_pb2>;
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pinctrl-names = "default";
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dmas = <&gpdma1 4 57 STM32_DMA_PERIPH_TX
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&gpdma1 5 57 STM32_DMA_PERIPH_RX>;
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dma-names = "tx", "rx";
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mx25lm51245: ospi-nor-flash@0 {
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compatible = "jedec,mspi-nor";
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reg = <0>;
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size = <DT_SIZE_M(512)>; /* 512 Mbits */
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status = "okay";
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read-command = <0xEE11>;
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write-command = <0x12ED>;
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rx-dummy = <20>;
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mspi-max-frequency = <DT_FREQ_M(50)>;
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mspi-io-mode = "MSPI_IO_MODE_OCTAL";
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mspi-data-rate = "MSPI_DATA_RATE_DUAL";
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mspi-hardware-ce-num = <0>;
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command-length = "INSTR_2_BYTE";
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jedec-id = [c2 85 3a];
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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slot0_partition: partition@0 {
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label = "nor";
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reg = <0x00000000 DT_SIZE_M(64)>;
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};
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};
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};
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};
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};
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};
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&gpdma1 {
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status = "okay";
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};

‎samples/drivers/mspi/mspi_flash/boards/stm32h735g_disco.conf‎

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CONFIG_LOG=y
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CONFIG_MSPI_LOG_LEVEL_INF=y
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CONFIG_ARM_MPU=n

‎samples/drivers/mspi/mspi_flash/boards/stm32h735g_disco.overlay‎

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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Replace the octospi1 by a "st,stm32-ospi-controller" compatible */
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/delete-node/ &octospi1;
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/ {
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aliases {
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flash0 = &mx25lm51245;
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};
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soc {
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octospi1: spi@52005000 {
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compatible = "st,stm32-ospi-controller";
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reg = <0x52005000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
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interrupts = <92 0>;
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clock-names = "ospix", "ospi-ker";
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clocks = <&rcc STM32_CLOCK(AHB3, 14)>,
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<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
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#address-cells = <1>;
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#size-cells = <0>;
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op-mode = "MSPI_OP_MODE_CONTROLLER";
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pinctrl-0 = <&octospim_p1_clk_pf10 &octospim_p1_ncs_pg6
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&octospim_p1_io0_pd11 &octospim_p1_io1_pd12
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&octospim_p1_io2_pe2 &octospim_p1_io3_pd13
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&octospim_p1_io4_pd4 &octospim_p1_io5_pd5
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&octospim_p1_io6_pg9 &octospim_p1_io7_pd7
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&octospim_p1_dqs_pb2>;
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pinctrl-names = "default";
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status = "okay";
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mx25lm51245: ospi-nor-flash@0 {
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compatible = "jedec,mspi-nor";
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reg = <0>;
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size = <DT_SIZE_M(512)>;
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status = "okay";
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mspi-max-frequency = <DT_FREQ_M(50)>;
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mspi-io-mode = "MSPI_IO_MODE_OCTAL";
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mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
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mspi-hardware-ce-num = <0>;
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read-command = <0xEC13>;
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write-command = <0x12ED>;
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command-length = "INSTR_2_BYTE";
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rx-dummy = <20>;
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jedec-id = [c2 85 3a];
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "nor";
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reg = <0x00000000 DT_SIZE_M(4)>;
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};
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};
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};
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};
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};
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};

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