arch: riscv: vexriscv: add VexRiscv cache driver

add driver for VexRiscv CPU cache controller.

Signed-off-by: Fin Maaß <[email protected]>

Author: maass-hamburg

arch/riscv/custom/CMakeLists.txt

@@ -6,4 +6,5 @@ add_subdirectory_ifdef(CONFIG_DT_HAS_OPENHWGROUP_CVA6_ENABLED openhwgroup/cva6)
 add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy)
+add_subdirectory_ifdef(CONFIG_DT_HAS_SPINALHDL_VEXRISCV_ENABLED vexriscv)
 add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead)

arch/riscv/custom/Kconfig

@@ -7,6 +7,12 @@ rsource "andes/Kconfig"
 
 endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
 
+if DT_HAS_SPINALHDL_VEXRISCV_ENABLED
+
+rsource "vexriscv/Kconfig"
+
+endif # DT_HAS_SPINALHDL_VEXRISCV_ENABLED
+
 if DT_HAS_XUANTIE_E907_ENABLED
 
 rsource "thead/Kconfig"

arch/riscv/custom/vexriscv/CMakeLists.txt

@@ -0,0 +1,4 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_VEXRISCV_CACHE cache_vexriscv.c)

arch/riscv/custom/vexriscv/Kconfig

@@ -0,0 +1,9 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config RISCV_CUSTOM_CSR_VEXRISCV_CACHE
+	bool
+	default y
+	depends on ARCH_CACHE
+	help
+	  This option enables cache support for VexRiscv family of CPUs.

arch/riscv/custom/vexriscv/cache_vexriscv.c

@@ -0,0 +1,122 @@
+/*
+ * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/cache.h>
+
+#ifdef CONFIG_DCACHE
+void arch_dcache_enable(void)
+{
+	/* Nothing */
+}
+
+void arch_dcache_disable(void)
+{
+	/* Nothing */
+}
+
+int arch_dcache_invd_all(void)
+{
+	/* Invalidate whole data cache instruction: 0x500F
+	 * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin
+	 */
+	__asm__ volatile(".insn 0x500F\n");
+
+	return 0;
+}
+
+int arch_dcache_invd_range(void *addr, size_t size)
+{
+	/* Invalidate cache line instruction: 0x500f | (rs1 << 15)
+	 * https://github.com/SpinalHDL/VexRiscv?tab=readme-ov-file#dbuscachedplugin
+	 */
+	__asm__ volatile(
+		"mv a0, %1\n"
+		"j 2f\n"
+		"3:\n"
+		".insn 0x5500F\n" /* 0x500f | (a0 << 15) */
+		"add a0, a0, %0\n"
+		"2:\n"
+		"bltu a0, %2, 3b\n"
+		: : "r"(CONFIG_DCACHE_LINE_SIZE),
+			"r"((unsigned int)(addr) & ~((CONFIG_DCACHE_LINE_SIZE) - 1UL)),
+			"r"((unsigned int)(addr) + (size))
+		: "a0");
+
+	return 0;
+}
+
+
+int arch_dcache_flush_all(void)
+{
+	/* VexRiscv cache is write-through */
+	return 0;
+}
+
+int arch_dcache_flush_range(void *addr __unused, size_t size __unused)
+{
+	return 0;
+}
+
+int arch_dcache_flush_and_invd_all(void)
+{
+	return arch_dcache_invd_all();
+}
+
+int arch_dcache_flush_and_invd_range(void *addr, size_t size)
+{
+	return arch_dcache_invd_range(addr, size);
+}
+#endif /* CONFIG_DCACHE */
+
+#ifdef CONFIG_ICACHE
+void arch_icache_enable(void)
+{
+	/* Nothing */
+}
+
+void arch_icache_disable(void)
+{
+	/* Nothing */
+}
+
+int arch_icache_flush_all(void)
+{
+	__asm__ volatile("fence.i\n");
+
+	return 0;
+}
+
+int arch_icache_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_invd_range(void *addr_in __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_and_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_range(void *addr __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_and_invd_range(void *addr __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+#endif /* CONFIG_ICACHE */
+
+void arch_cache_init(void)
+{
+	/* Nothing */
+}

dts/bindings/cpu/litex,vexriscv-standard.yaml

@@ -6,4 +6,10 @@ description: VexRiscv core with the standard configuration as used by LiteX
 
 compatible: "litex,vexriscv-standard"
 
-include: riscv,cpus.yaml
+include: spinalhdl,vexriscv.yaml
+
+properties:
+  i-cache-line-size:
+    default: 32
+  d-cache-line-size:
+    default: 32

dts/bindings/cpu/spinalhdl,vexriscv.yaml

@@ -0,0 +1,8 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+description: VexRiscv core
+
+compatible: "spinalhdl,vexriscv"
+
+include: riscv,cpus.yaml

dts/riscv/riscv32-litex-vexriscv.dtsi

@@ -22,7 +22,7 @@
 
 		cpu0: cpu@0 {
 			clock-frequency = <100000000>;
-			compatible = "litex,vexriscv-standard", "riscv";
+			compatible = "litex,vexriscv-standard", "spinalhdl,vexriscv", "riscv";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32im_zicsr_zifencei";

soc/litex/litex_vexriscv/Kconfig

@@ -8,6 +8,9 @@ config SOC_LITEX_VEXRISCV
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	# There are varriants of the Vexriscv without cache, be able to set it
+	select CPU_HAS_ICACHE if $(dt_node_int_prop_int,/cpus/cpu@0,i-cache-line-size) > 0
+	select CPU_HAS_DCACHE if $(dt_node_int_prop_int,/cpus/cpu@0,d-cache-line-size) > 0
 	imply XIP
 
 if SOC_LITEX_VEXRISCV