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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Core Devices LLC |
| 3 | + * SPDX-License-Identifier: Apache-2.0 |
| 4 | + */ |
| 5 | + |
| 6 | +/dts-v1/; |
| 7 | + |
| 8 | +#include <sifli/sf32lb52x.dtsi> |
| 9 | +#include <sifli/sf32lb52x-ram012.dtsi> |
| 10 | +#include <zephyr/dt-bindings/dma/sf32lb52x-dma.h> |
| 11 | +#include <zephyr/dt-bindings/gpio/gpio.h> |
| 12 | +#include <zephyr/dt-bindings/input/input-event-codes.h> |
| 13 | + |
| 14 | +#include "pt2-pinctrl.dtsi" |
| 15 | + |
| 16 | +/ { |
| 17 | + model = "Core Devices Pebble Time 2"; |
| 18 | + compatible = "coredevices,pt2"; |
| 19 | + |
| 20 | + #address-cells = <1>; |
| 21 | + #size-cells = <1>; |
| 22 | + |
| 23 | + chosen { |
| 24 | + zephyr,flash = &gd25q256e; |
| 25 | + zephyr,flash-controller = &mpi2; |
| 26 | + zephyr,code-partition = &code; |
| 27 | + zephyr,console = &usart1; |
| 28 | + zephyr,shell-uart = &usart1; |
| 29 | + }; |
| 30 | + |
| 31 | + buttons { |
| 32 | + compatible = "gpio-keys"; |
| 33 | + |
| 34 | + btn_back: button-back { |
| 35 | + label = "BACK"; |
| 36 | + gpios = <&gpioa_32_44 2 GPIO_ACTIVE_HIGH>; |
| 37 | + zephyr,code = <INPUT_KEY_BACK>; |
| 38 | + }; |
| 39 | + |
| 40 | + btn_up: button-up { |
| 41 | + label = "UP"; |
| 42 | + gpios = <&gpioa_32_44 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
| 43 | + zephyr,code = <INPUT_KEY_UP>; |
| 44 | + }; |
| 45 | + |
| 46 | + btn_center: button-center { |
| 47 | + label = "CENTER"; |
| 48 | + gpios = <&gpioa_32_44 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
| 49 | + zephyr,code = <INPUT_KEY_ENTER>; |
| 50 | + }; |
| 51 | + |
| 52 | + btn_down: button-down { |
| 53 | + label = "DOWN"; |
| 54 | + gpios = <&gpioa_32_44 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
| 55 | + zephyr,code = <INPUT_KEY_DOWN>; |
| 56 | + }; |
| 57 | + }; |
| 58 | + |
| 59 | + alias { |
| 60 | + sw0 = &btn_back; |
| 61 | + sw1 = &btn_up; |
| 62 | + watchdog0 = &wdt; |
| 63 | + }; |
| 64 | +}; |
| 65 | + |
| 66 | +&cpu0 { |
| 67 | + clock-frequency = <DT_FREQ_M(240)>; |
| 68 | +}; |
| 69 | + |
| 70 | +&dmac { |
| 71 | + status = "okay"; |
| 72 | +}; |
| 73 | + |
| 74 | +&gpioa_32_44 { |
| 75 | + status = "okay"; |
| 76 | +}; |
| 77 | + |
| 78 | +&hxt48 { |
| 79 | + status = "okay"; |
| 80 | +}; |
| 81 | + |
| 82 | +&mpi2 { |
| 83 | + compatible = "sifli,sf32lb-mpi-qspi-nor"; |
| 84 | + dmas = <&dmac 0 SF32LB52X_DMA_REQ_MPI2 SF32LB_DMA_PL_MEDIUM>; |
| 85 | + sifli,lines = <4>; |
| 86 | + sifli,psclr = <0>; |
| 87 | + status = "okay"; |
| 88 | + |
| 89 | + gd25q256e: flash@0 { |
| 90 | + compatible = "gd,gd25q256e", "jedec,qspi-nor"; |
| 91 | + reg = <0x0>; |
| 92 | + size = <DT_SIZE_M(256)>; |
| 93 | + quad-enable-requirements = "S2B1v6"; |
| 94 | + |
| 95 | + partitions { |
| 96 | + compatible = "fixed-partitions"; |
| 97 | + #address-cells = <1>; |
| 98 | + #size-cells = <1>; |
| 99 | + |
| 100 | + ptable: partition@0 { |
| 101 | + label = "ptable"; |
| 102 | + reg = <0x0 DT_SIZE_K(64)>; |
| 103 | + }; |
| 104 | + |
| 105 | + code: partition@10000 { |
| 106 | + label = "code"; |
| 107 | + reg = <0x10000 DT_SIZE_K(32704)>; |
| 108 | + }; |
| 109 | + }; |
| 110 | + }; |
| 111 | +}; |
| 112 | + |
| 113 | +&pinctrl { |
| 114 | + status = "okay"; |
| 115 | +}; |
| 116 | + |
| 117 | +&rcc_clk { |
| 118 | + status = "okay"; |
| 119 | + |
| 120 | + sifli,hdiv = <1>; |
| 121 | + sifli,pdiv1 = <1>; |
| 122 | + sifli,pdiv2 = <6>; |
| 123 | + |
| 124 | + dll1 { |
| 125 | + status = "okay"; |
| 126 | + clock-frequency = <DT_FREQ_M(240)>; |
| 127 | + }; |
| 128 | +}; |
| 129 | + |
| 130 | +&usart1 { |
| 131 | + status = "okay"; |
| 132 | + current-speed = <1000000>; |
| 133 | + pinctrl-0 = <&usart1_default>; |
| 134 | + pinctrl-names = "default"; |
| 135 | +}; |
| 136 | + |
| 137 | +&wdt { |
| 138 | + status = "okay"; |
| 139 | +}; |
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