ld: Reset linker '.' value after .ER_CODE_SRAM section

When processing the .ER_CODE_SRAM section, the location counter is set
to the VMA of that section, so after processing the next section will
use that VMA instead of the next available address in the FLASH
region.

Reset the location counter to the next available FLASH address after
processing this section will ensure that any subsequent FLASH data
is placed in the correct location.

This test fails without this patch:

$ west build -p -b lpcxpresso55s69/lpc55s69/cpu0/ns \
  samples/synchronization -T sample.kernel.synchronization

.../ld: address 0x14003e84 of bin/tfm_s.axf section `.ER_TFM_CODE'
    is not within region `FLASH'
.../ld: address 0x14005c20 of bin/tfm_s.axf section `.TFM_UNPRIV_CODE'
    is not within region `FLASH'
.../ld: bin/tfm_s.axf section `.TFM_PSA_ROT_LINKER_DATA'
    will not fit in region `FLASH'
.../ld: address 0x14003e84 of bin/tfm_s.axf section `.ER_TFM_CODE'
    is not within region `FLASH'
.../ld: address 0x14005c20 of bin/tfm_s.axf section `.TFM_UNPRIV_CODE'
    is not within region `FLASH'
.../ld: ERROR: CMSE stub (.gnu.sgstubs section) too far (0x10008540)
    from destination (0x14003ee4)

Note that the linker is generating addresses within the CODE_RAM
memory region rather than the FLASH region.

Signed-off-by: Keith Packard <[email protected]>

Author: keith-packard

platform/ext/common/gcc/tfm_common_s.ld.template

@@ -192,6 +192,9 @@ SECTIONS
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
 
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     ASSERT(S_RAM_CODE_START % 4 == 0, "S_RAM_CODE_START must be divisible by 4")
 
     Image$$ER_CODE_SRAM$$RO$$Base = ADDR(.ER_CODE_SRAM);

platform/ext/common/gcc/tfm_isolation_s.ld.template

@@ -337,6 +337,9 @@ SECTIONS
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
 
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     ASSERT(S_RAM_CODE_START % 4 == 0, "S_RAM_CODE_START must be divisible by 4")
 
     Image$$ER_CODE_SRAM$$RO$$Base = ADDR(.ER_CODE_SRAM);

platform/ext/common/llvm/tfm_isolation_s.ld.template

@@ -303,6 +303,9 @@ SECTIONS
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
 
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     ASSERT(S_RAM_CODE_START % 4 == 0, "S_RAM_CODE_START must be divisible by 4")
 
     Image$$ER_CODE_SRAM$$RO$$Base = ADDR(.ER_CODE_SRAM);

platform/ext/target/arm/musca_b1/Device/Source/gcc/musca_bl2.ld

@@ -58,6 +58,10 @@ SECTIONS
         *libflash_drivers.o(.rodata*)
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
+
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     Image$$ER_CODE_SRAM$$Base = ADDR(.ER_CODE_SRAM);
     Image$$ER_CODE_SRAM$$Limit = ADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
 

platform/ext/target/arm/musca_b1/Device/Source/llvm/musca_bl2.ld

@@ -57,6 +57,10 @@ SECTIONS
         *libflash_drivers.o(.rodata*)
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
+
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     Image$$ER_CODE_SRAM$$Base = ADDR(.ER_CODE_SRAM);
     Image$$ER_CODE_SRAM$$Limit = ADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
 

platform/ext/target/rpi/rp2350/linker_s.ld

@@ -150,6 +150,9 @@ SECTIONS
         . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */
     } > CODE_RAM AT > FLASH
 
+    /* Reset current position for subsequent sections */
+    . = LOADADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM);
+
     ASSERT(S_RAM_CODE_START % 4 == 0, "S_RAM_CODE_START must be divisible by 4")
 
     Image$$ER_CODE_SRAM$$RO$$Base = ADDR(.ER_CODE_SRAM);